0001 /*
0002 * MPC8544 Silicon/SoC Device Tree Source (post include)
0003 *
0004 * Copyright 2011 Freescale Semiconductor Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0024 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0025 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0026 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0027 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0028 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0029 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0030 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033 */
0034
0035 &lbc {
0036 #address-cells = <2>;
0037 #size-cells = <1>;
0038 compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
0039 interrupts = <19 2 0 0>;
0040 };
0041
0042 /* controller at 0x8000 */
0043 &pci0 {
0044 compatible = "fsl,mpc8540-pci";
0045 device_type = "pci";
0046 interrupts = <24 0x2 0 0>;
0047 bus-range = <0 0xff>;
0048 #interrupt-cells = <1>;
0049 #size-cells = <2>;
0050 #address-cells = <3>;
0051 };
0052
0053 /* controller at 0x9000 */
0054 &pci1 {
0055 compatible = "fsl,mpc8548-pcie";
0056 device_type = "pci";
0057 #size-cells = <2>;
0058 #address-cells = <3>;
0059 bus-range = <0 255>;
0060 clock-frequency = <33333333>;
0061 interrupts = <25 2 0 0>;
0062
0063 pcie@0 {
0064 reg = <0 0 0 0 0>;
0065 #interrupt-cells = <1>;
0066 #size-cells = <2>;
0067 #address-cells = <3>;
0068 device_type = "pci";
0069 interrupts = <25 2 0 0>;
0070 interrupt-map-mask = <0xf800 0 0 7>;
0071
0072 interrupt-map = <
0073 /* IDSEL 0x0 */
0074 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
0075 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
0076 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
0077 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
0078 >;
0079 };
0080 };
0081
0082 /* controller at 0xa000 */
0083 &pci2 {
0084 compatible = "fsl,mpc8548-pcie";
0085 device_type = "pci";
0086 #size-cells = <2>;
0087 #address-cells = <3>;
0088 bus-range = <0 255>;
0089 clock-frequency = <33333333>;
0090 interrupts = <26 2 0 0>;
0091
0092 pcie@0 {
0093 reg = <0 0 0 0 0>;
0094 #interrupt-cells = <1>;
0095 #size-cells = <2>;
0096 #address-cells = <3>;
0097 device_type = "pci";
0098 interrupts = <26 2 0 0>;
0099 interrupt-map-mask = <0xf800 0 0 7>;
0100 interrupt-map = <
0101 /* IDSEL 0x0 */
0102 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
0103 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
0104 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
0105 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
0106 >;
0107 };
0108 };
0109
0110 /* controller at 0xb000 */
0111 &pci3 {
0112 compatible = "fsl,mpc8548-pcie";
0113 device_type = "pci";
0114 #size-cells = <2>;
0115 #address-cells = <3>;
0116 bus-range = <0 255>;
0117 clock-frequency = <33333333>;
0118 interrupts = <27 2 0 0>;
0119
0120 pcie@0 {
0121 reg = <0 0 0 0 0>;
0122 #interrupt-cells = <1>;
0123 #size-cells = <2>;
0124 #address-cells = <3>;
0125 device_type = "pci";
0126 interrupts = <27 2 0 0>;
0127 interrupt-map-mask = <0xf800 0 0 7>;
0128 interrupt-map = <
0129 /* IDSEL 0x0 */
0130 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
0131 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
0132 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
0133 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
0134 >;
0135 };
0136 };
0137
0138 &soc {
0139 #address-cells = <1>;
0140 #size-cells = <1>;
0141 device_type = "soc";
0142 compatible = "fsl,mpc8544-immr", "simple-bus";
0143 bus-frequency = <0>; // Filled out by uboot.
0144
0145 ecm-law@0 {
0146 compatible = "fsl,ecm-law";
0147 reg = <0x0 0x1000>;
0148 fsl,num-laws = <10>;
0149 };
0150
0151 ecm@1000 {
0152 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
0153 reg = <0x1000 0x1000>;
0154 interrupts = <17 2 0 0>;
0155 };
0156
0157 memory-controller@2000 {
0158 compatible = "fsl,mpc8544-memory-controller";
0159 reg = <0x2000 0x1000>;
0160 interrupts = <18 2 0 0>;
0161 };
0162
0163 /include/ "pq3-i2c-0.dtsi"
0164 /include/ "pq3-i2c-1.dtsi"
0165 /include/ "pq3-duart-0.dtsi"
0166
0167 L2: l2-cache-controller@20000 {
0168 compatible = "fsl,mpc8544-l2-cache-controller";
0169 reg = <0x20000 0x1000>;
0170 cache-line-size = <32>; // 32 bytes
0171 cache-size = <0x40000>; // L2, 256K
0172 interrupts = <16 2 0 0>;
0173 };
0174
0175 /include/ "pq3-dma-0.dtsi"
0176 /include/ "pq3-etsec1-0.dtsi"
0177 /include/ "pq3-etsec1-2.dtsi"
0178
0179 ethernet@26000 {
0180 cell-index = <1>;
0181 };
0182
0183 /include/ "pq3-sec2.1-0.dtsi"
0184 /include/ "pq3-mpic.dtsi"
0185
0186 global-utilities@e0000 {
0187 compatible = "fsl,mpc8544-guts";
0188 reg = <0xe0000 0x1000>;
0189 fsl,has-rstcr;
0190 };
0191 };
