0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * MPC8540 ADS Device Tree Source
0004 *
0005 * Copyright 2006, 2008 Freescale Semiconductor Inc.
0006 */
0007
0008 /dts-v1/;
0009
0010 /include/ "e500v2_power_isa.dtsi"
0011
0012 / {
0013 model = "MPC8540ADS";
0014 compatible = "MPC8540ADS", "MPC85xxADS";
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017
0018 aliases {
0019 ethernet0 = &enet0;
0020 ethernet1 = &enet1;
0021 ethernet2 = &enet2;
0022 serial0 = &serial0;
0023 serial1 = &serial1;
0024 pci0 = &pci0;
0025 };
0026
0027 cpus {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030
0031 PowerPC,8540@0 {
0032 device_type = "cpu";
0033 reg = <0x0>;
0034 d-cache-line-size = <32>; // 32 bytes
0035 i-cache-line-size = <32>; // 32 bytes
0036 d-cache-size = <0x8000>; // L1, 32K
0037 i-cache-size = <0x8000>; // L1, 32K
0038 timebase-frequency = <0>; // 33 MHz, from uboot
0039 bus-frequency = <0>; // 166 MHz
0040 clock-frequency = <0>; // 825 MHz, from uboot
0041 next-level-cache = <&L2>;
0042 };
0043 };
0044
0045 memory {
0046 device_type = "memory";
0047 reg = <0x0 0x8000000>; // 128M at 0x0
0048 };
0049
0050 soc8540@e0000000 {
0051 #address-cells = <1>;
0052 #size-cells = <1>;
0053 device_type = "soc";
0054 compatible = "simple-bus";
0055 ranges = <0x0 0xe0000000 0x100000>;
0056 bus-frequency = <0>;
0057
0058 ecm-law@0 {
0059 compatible = "fsl,ecm-law";
0060 reg = <0x0 0x1000>;
0061 fsl,num-laws = <8>;
0062 };
0063
0064 ecm@1000 {
0065 compatible = "fsl,mpc8540-ecm", "fsl,ecm";
0066 reg = <0x1000 0x1000>;
0067 interrupts = <17 2>;
0068 interrupt-parent = <&mpic>;
0069 };
0070
0071 memory-controller@2000 {
0072 compatible = "fsl,mpc8540-memory-controller";
0073 reg = <0x2000 0x1000>;
0074 interrupt-parent = <&mpic>;
0075 interrupts = <18 2>;
0076 };
0077
0078 L2: l2-cache-controller@20000 {
0079 compatible = "fsl,mpc8540-l2-cache-controller";
0080 reg = <0x20000 0x1000>;
0081 cache-line-size = <32>; // 32 bytes
0082 cache-size = <0x40000>; // L2, 256K
0083 interrupt-parent = <&mpic>;
0084 interrupts = <16 2>;
0085 };
0086
0087 i2c@3000 {
0088 #address-cells = <1>;
0089 #size-cells = <0>;
0090 cell-index = <0>;
0091 compatible = "fsl-i2c";
0092 reg = <0x3000 0x100>;
0093 interrupts = <43 2>;
0094 interrupt-parent = <&mpic>;
0095 dfsrr;
0096 };
0097
0098 dma@21300 {
0099 #address-cells = <1>;
0100 #size-cells = <1>;
0101 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
0102 reg = <0x21300 0x4>;
0103 ranges = <0x0 0x21100 0x200>;
0104 cell-index = <0>;
0105 dma-channel@0 {
0106 compatible = "fsl,mpc8540-dma-channel",
0107 "fsl,eloplus-dma-channel";
0108 reg = <0x0 0x80>;
0109 cell-index = <0>;
0110 interrupt-parent = <&mpic>;
0111 interrupts = <20 2>;
0112 };
0113 dma-channel@80 {
0114 compatible = "fsl,mpc8540-dma-channel",
0115 "fsl,eloplus-dma-channel";
0116 reg = <0x80 0x80>;
0117 cell-index = <1>;
0118 interrupt-parent = <&mpic>;
0119 interrupts = <21 2>;
0120 };
0121 dma-channel@100 {
0122 compatible = "fsl,mpc8540-dma-channel",
0123 "fsl,eloplus-dma-channel";
0124 reg = <0x100 0x80>;
0125 cell-index = <2>;
0126 interrupt-parent = <&mpic>;
0127 interrupts = <22 2>;
0128 };
0129 dma-channel@180 {
0130 compatible = "fsl,mpc8540-dma-channel",
0131 "fsl,eloplus-dma-channel";
0132 reg = <0x180 0x80>;
0133 cell-index = <3>;
0134 interrupt-parent = <&mpic>;
0135 interrupts = <23 2>;
0136 };
0137 };
0138
0139 enet0: ethernet@24000 {
0140 #address-cells = <1>;
0141 #size-cells = <1>;
0142 cell-index = <0>;
0143 device_type = "network";
0144 model = "TSEC";
0145 compatible = "gianfar";
0146 reg = <0x24000 0x1000>;
0147 ranges = <0x0 0x24000 0x1000>;
0148 local-mac-address = [ 00 00 00 00 00 00 ];
0149 interrupts = <29 2 30 2 34 2>;
0150 interrupt-parent = <&mpic>;
0151 tbi-handle = <&tbi0>;
0152 phy-handle = <&phy0>;
0153
0154 mdio@520 {
0155 #address-cells = <1>;
0156 #size-cells = <0>;
0157 compatible = "fsl,gianfar-mdio";
0158 reg = <0x520 0x20>;
0159
0160 phy0: ethernet-phy@0 {
0161 interrupt-parent = <&mpic>;
0162 interrupts = <5 1>;
0163 reg = <0x0>;
0164 };
0165 phy1: ethernet-phy@1 {
0166 interrupt-parent = <&mpic>;
0167 interrupts = <5 1>;
0168 reg = <0x1>;
0169 };
0170 phy3: ethernet-phy@3 {
0171 interrupt-parent = <&mpic>;
0172 interrupts = <7 1>;
0173 reg = <0x3>;
0174 };
0175 tbi0: tbi-phy@11 {
0176 reg = <0x11>;
0177 device_type = "tbi-phy";
0178 };
0179 };
0180 };
0181
0182 enet1: ethernet@25000 {
0183 #address-cells = <1>;
0184 #size-cells = <1>;
0185 cell-index = <1>;
0186 device_type = "network";
0187 model = "TSEC";
0188 compatible = "gianfar";
0189 reg = <0x25000 0x1000>;
0190 ranges = <0x0 0x25000 0x1000>;
0191 local-mac-address = [ 00 00 00 00 00 00 ];
0192 interrupts = <35 2 36 2 40 2>;
0193 interrupt-parent = <&mpic>;
0194 tbi-handle = <&tbi1>;
0195 phy-handle = <&phy1>;
0196
0197 mdio@520 {
0198 #address-cells = <1>;
0199 #size-cells = <0>;
0200 compatible = "fsl,gianfar-tbi";
0201 reg = <0x520 0x20>;
0202
0203 tbi1: tbi-phy@11 {
0204 reg = <0x11>;
0205 device_type = "tbi-phy";
0206 };
0207 };
0208 };
0209
0210 enet2: ethernet@26000 {
0211 #address-cells = <1>;
0212 #size-cells = <1>;
0213 cell-index = <2>;
0214 device_type = "network";
0215 model = "FEC";
0216 compatible = "gianfar";
0217 reg = <0x26000 0x1000>;
0218 ranges = <0x0 0x26000 0x1000>;
0219 local-mac-address = [ 00 00 00 00 00 00 ];
0220 interrupts = <41 2>;
0221 interrupt-parent = <&mpic>;
0222 tbi-handle = <&tbi2>;
0223 phy-handle = <&phy3>;
0224
0225 mdio@520 {
0226 #address-cells = <1>;
0227 #size-cells = <0>;
0228 compatible = "fsl,gianfar-tbi";
0229 reg = <0x520 0x20>;
0230
0231 tbi2: tbi-phy@11 {
0232 reg = <0x11>;
0233 device_type = "tbi-phy";
0234 };
0235 };
0236 };
0237
0238 serial0: serial@4500 {
0239 cell-index = <0>;
0240 device_type = "serial";
0241 compatible = "fsl,ns16550", "ns16550";
0242 reg = <0x4500 0x100>; // reg base, size
0243 clock-frequency = <0>; // should we fill in in uboot?
0244 interrupts = <42 2>;
0245 interrupt-parent = <&mpic>;
0246 };
0247
0248 serial1: serial@4600 {
0249 cell-index = <1>;
0250 device_type = "serial";
0251 compatible = "fsl,ns16550", "ns16550";
0252 reg = <0x4600 0x100>; // reg base, size
0253 clock-frequency = <0>; // should we fill in in uboot?
0254 interrupts = <42 2>;
0255 interrupt-parent = <&mpic>;
0256 };
0257 mpic: pic@40000 {
0258 interrupt-controller;
0259 #address-cells = <0>;
0260 #interrupt-cells = <2>;
0261 reg = <0x40000 0x40000>;
0262 compatible = "chrp,open-pic";
0263 device_type = "open-pic";
0264 };
0265 };
0266
0267 pci0: pci@e0008000 {
0268 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0269 interrupt-map = <
0270
0271 /* IDSEL 0x02 */
0272 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
0273 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
0274 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
0275 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
0276
0277 /* IDSEL 0x03 */
0278 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
0279 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
0280 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
0281 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
0282
0283 /* IDSEL 0x04 */
0284 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
0285 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
0286 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
0287 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
0288
0289 /* IDSEL 0x05 */
0290 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
0291 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
0292 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
0293 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
0294
0295 /* IDSEL 0x0c */
0296 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
0297 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
0298 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
0299 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
0300
0301 /* IDSEL 0x0d */
0302 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
0303 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
0304 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
0305 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
0306
0307 /* IDSEL 0x0e */
0308 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
0309 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
0310 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
0311 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
0312
0313 /* IDSEL 0x0f */
0314 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
0315 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
0316 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
0317 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
0318
0319 /* IDSEL 0x12 */
0320 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
0321 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
0322 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
0323 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
0324
0325 /* IDSEL 0x13 */
0326 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
0327 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
0328 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
0329 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
0330
0331 /* IDSEL 0x14 */
0332 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
0333 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
0334 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
0335 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
0336
0337 /* IDSEL 0x15 */
0338 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
0339 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
0340 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
0341 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
0342 interrupt-parent = <&mpic>;
0343 interrupts = <24 2>;
0344 bus-range = <0 0>;
0345 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0346 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
0347 clock-frequency = <66666666>;
0348 #interrupt-cells = <1>;
0349 #size-cells = <2>;
0350 #address-cells = <3>;
0351 reg = <0xe0008000 0x1000>;
0352 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
0353 device_type = "pci";
0354 };
0355 };
