0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
0004 *
0005 * (C) Copyright 2014
0006 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
0007 *
0008 * Copyright 2011 Freescale Semiconductor Inc.
0009 */
0010
0011 /include/ "p2041si-pre.dtsi"
0012
0013 / {
0014 model = "keymile,kmcoge4";
0015 compatible = "keymile,kmcoge4", "keymile,kmp204x";
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018 interrupt-parent = <&mpic>;
0019
0020 memory {
0021 device_type = "memory";
0022 };
0023
0024 reserved-memory {
0025 #address-cells = <2>;
0026 #size-cells = <2>;
0027 ranges;
0028
0029 bman_fbpr: bman-fbpr {
0030 size = <0 0x1000000>;
0031 alignment = <0 0x1000000>;
0032 };
0033 qman_fqd: qman-fqd {
0034 size = <0 0x400000>;
0035 alignment = <0 0x400000>;
0036 };
0037 qman_pfdr: qman-pfdr {
0038 size = <0 0x2000000>;
0039 alignment = <0 0x2000000>;
0040 };
0041 };
0042
0043 dcsr: dcsr@f00000000 {
0044 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
0045 };
0046
0047 bportals: bman-portals@ff4000000 {
0048 ranges = <0x0 0xf 0xf4000000 0x200000>;
0049 };
0050
0051 qportals: qman-portals@ff4200000 {
0052 ranges = <0x0 0xf 0xf4200000 0x200000>;
0053 };
0054
0055 soc: soc@ffe000000 {
0056 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
0057 reg = <0xf 0xfe000000 0 0x00001000>;
0058 spi@110000 {
0059 flash@0 {
0060 #address-cells = <1>;
0061 #size-cells = <1>;
0062 compatible = "spansion,s25fl256s1", "jedec,spi-nor";
0063 reg = <0>;
0064 spi-max-frequency = <20000000>; /* input clock */
0065 };
0066
0067 network_clock@1 {
0068 compatible = "zarlink,zl30343";
0069 reg = <1>;
0070 spi-max-frequency = <8000000>;
0071 };
0072
0073 flash@2 {
0074 #address-cells = <1>;
0075 #size-cells = <1>;
0076 compatible = "micron,m25p32", "jedec,spi-nor";
0077 reg = <2>;
0078 spi-max-frequency = <15000000>;
0079 };
0080 };
0081
0082 sdhc@114000 {
0083 status = "disabled";
0084 };
0085
0086 i2c@119000 {
0087 status = "disabled";
0088 };
0089
0090 i2c@119100 {
0091 status = "disabled";
0092 };
0093
0094 usb0: usb@210000 {
0095 status = "disabled";
0096 };
0097
0098 usb1: usb@211000 {
0099 status = "disabled";
0100 };
0101
0102 sata@220000 {
0103 status = "disabled";
0104 };
0105
0106 sata@221000 {
0107 status = "disabled";
0108 };
0109
0110 fman0: fman@400000 {
0111 enet0: ethernet@e0000 {
0112 phy-connection-type = "sgmii";
0113 fixed-link {
0114 speed = <1000>;
0115 full-duplex;
0116 };
0117 };
0118 mdio0: mdio@e1120 {
0119 front_phy: ethernet-phy@11 {
0120 reg = <0x11>;
0121 };
0122 };
0123
0124 enet1: ethernet@e2000 {
0125 phy-connection-type = "sgmii";
0126 fixed-link {
0127 speed = <1000>;
0128 full-duplex;
0129 };
0130 };
0131 enet2: ethernet@e4000 {
0132 status = "disabled";
0133 };
0134
0135 enet3: ethernet@e6000 {
0136 status = "disabled";
0137 };
0138 enet4: ethernet@e8000 {
0139 phy-handle = <&front_phy>;
0140 phy-connection-type = "rgmii";
0141 };
0142 enet5: ethernet@f0000 {
0143 status = "disabled";
0144 };
0145 };
0146 };
0147
0148 rio: rapidio@ffe0c0000 {
0149 status = "disabled";
0150 };
0151
0152 lbc: localbus@ffe124000 {
0153 reg = <0xf 0xfe124000 0 0x1000>;
0154 ranges = <0 0 0xf 0xffa00000 0x00040000 /* LB 0 */
0155 1 0 0xf 0xfb000000 0x00010000 /* LB 1 */
0156 2 0 0xf 0xd0000000 0x10000000 /* LB 2 */
0157 3 0 0xf 0xe0000000 0x10000000>; /* LB 3 */
0158
0159 nand@0,0 {
0160 #address-cells = <1>;
0161 #size-cells = <1>;
0162 compatible = "fsl,elbc-fcm-nand";
0163 reg = <0 0 0x40000>;
0164 };
0165
0166 board-control@1,0 {
0167 compatible = "keymile,qriox";
0168 reg = <1 0 0x80>;
0169 };
0170
0171 chassis-mgmt@3,0 {
0172 compatible = "keymile,bfticu";
0173 interrupt-controller;
0174 #interrupt-cells = <2>;
0175 reg = <3 0 0x100>;
0176 interrupt-parent = <&mpic>;
0177 interrupts = <6 1 0 0>;
0178 };
0179 };
0180
0181 pci0: pcie@ffe200000 {
0182 reg = <0xf 0xfe200000 0 0x1000>;
0183 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0184 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
0185 pcie@0 {
0186 ranges = <0x02000000 0 0xe0000000
0187 0x02000000 0 0xe0000000
0188 0 0x20000000
0189
0190 0x01000000 0 0x00000000
0191 0x01000000 0 0x00000000
0192 0 0x00010000>;
0193 };
0194 };
0195
0196 pci1: pcie@ffe201000 {
0197 status = "disabled";
0198 };
0199
0200 pci2: pcie@ffe202000 {
0201 reg = <0xf 0xfe202000 0 0x1000>;
0202 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
0203 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
0204 pcie@0 {
0205 ranges = <0x02000000 0 0xe0000000
0206 0x02000000 0 0xe0000000
0207 0 0x20000000
0208
0209 0x01000000 0 0x00000000
0210 0x01000000 0 0x00000000
0211 0 0x00010000>;
0212 };
0213 };
0214 };
0215
0216 /include/ "p2041si-post.dtsi"
