0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Cyrus 5020 Device Tree Source, based on p5020ds.dts
0004 *
0005 * Copyright 2015 Andy Fleming
0006 *
0007 * p5020ds.dts copyright:
0008 * Copyright 2010 - 2014 Freescale Semiconductor Inc.
0009 */
0010
0011 /include/ "p5020si-pre.dtsi"
0012
0013 / {
0014 model = "varisys,CYRUS";
0015 compatible = "varisys,CYRUS";
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018 interrupt-parent = <&mpic>;
0019
0020 memory {
0021 device_type = "memory";
0022 };
0023
0024 reserved-memory {
0025 #address-cells = <2>;
0026 #size-cells = <2>;
0027 ranges;
0028
0029 bman_fbpr: bman-fbpr {
0030 size = <0 0x1000000>;
0031 alignment = <0 0x1000000>;
0032 };
0033 qman_fqd: qman-fqd {
0034 size = <0 0x400000>;
0035 alignment = <0 0x400000>;
0036 };
0037 qman_pfdr: qman-pfdr {
0038 size = <0 0x2000000>;
0039 alignment = <0 0x2000000>;
0040 };
0041 };
0042
0043 dcsr: dcsr@f00000000 {
0044 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
0045 };
0046
0047 bportals: bman-portals@ff4000000 {
0048 ranges = <0x0 0xf 0xf4000000 0x200000>;
0049 };
0050
0051 qportals: qman-portals@ff4200000 {
0052 ranges = <0x0 0xf 0xf4200000 0x200000>;
0053 };
0054
0055 soc: soc@ffe000000 {
0056 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
0057 reg = <0xf 0xfe000000 0 0x00001000>;
0058 spi@110000 {
0059 };
0060
0061 i2c@118100 {
0062 };
0063
0064 i2c@119100 {
0065 rtc@6f {
0066 compatible = "microchip,mcp7941x";
0067 reg = <0x6f>;
0068 };
0069 };
0070 };
0071
0072 rio: rapidio@ffe0c0000 {
0073 reg = <0xf 0xfe0c0000 0 0x11000>;
0074
0075 port1 {
0076 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
0077 };
0078 port2 {
0079 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
0080 };
0081 };
0082
0083 lbc: localbus@ffe124000 {
0084 reg = <0xf 0xfe124000 0 0x1000>;
0085 ranges = <0 0 0xf 0xe8000000 0x08000000
0086 2 0 0xf 0xffa00000 0x00040000
0087 3 0 0xf 0xffdf0000 0x00008000>;
0088 };
0089
0090 pci0: pcie@ffe200000 {
0091 reg = <0xf 0xfe200000 0 0x1000>;
0092 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0093 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
0094 pcie@0 {
0095 ranges = <0x02000000 0 0xe0000000
0096 0x02000000 0 0xe0000000
0097 0 0x20000000
0098
0099 0x01000000 0 0x00000000
0100 0x01000000 0 0x00000000
0101 0 0x00010000>;
0102 };
0103 };
0104
0105 pci1: pcie@ffe201000 {
0106 reg = <0xf 0xfe201000 0 0x1000>;
0107 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0108 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
0109 pcie@0 {
0110 ranges = <0x02000000 0 0xe0000000
0111 0x02000000 0 0xe0000000
0112 0 0x20000000
0113
0114 0x01000000 0 0x00000000
0115 0x01000000 0 0x00000000
0116 0 0x00010000>;
0117 };
0118 };
0119
0120 pci2: pcie@ffe202000 {
0121 reg = <0xf 0xfe202000 0 0x1000>;
0122 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0123 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
0124 pcie@0 {
0125 ranges = <0x02000000 0 0xe0000000
0126 0x02000000 0 0xe0000000
0127 0 0x20000000
0128
0129 0x01000000 0 0x00000000
0130 0x01000000 0 0x00000000
0131 0 0x00010000>;
0132 };
0133 };
0134
0135 pci3: pcie@ffe203000 {
0136 reg = <0xf 0xfe203000 0 0x1000>;
0137 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
0138 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
0139 pcie@0 {
0140 ranges = <0x02000000 0 0xe0000000
0141 0x02000000 0 0xe0000000
0142 0 0x20000000
0143
0144 0x01000000 0 0x00000000
0145 0x01000000 0 0x00000000
0146 0 0x00010000>;
0147 };
0148 };
0149 };
0150
0151 /include/ "p5020si-post.dtsi"
