0001 /*
0002 * B4420 Silicon/SoC Device Tree Source (pre include)
0003 *
0004 * Copyright 2012 - 2015 Freescale Semiconductor, Inc.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions are met:
0008 * * Redistributions of source code must retain the above copyright
0009 * notice, this list of conditions and the following disclaimer.
0010 * * Redistributions in binary form must reproduce the above copyright
0011 * notice, this list of conditions and the following disclaimer in the
0012 * documentation and/or other materials provided with the distribution.
0013 * * Neither the name of Freescale Semiconductor nor the
0014 * names of its contributors may be used to endorse or promote products
0015 * derived from this software without specific prior written permission.
0016 *
0017 *
0018 * ALTERNATIVELY, this software may be distributed under the terms of the
0019 * GNU General Public License ("GPL") as published by the Free Software
0020 * Foundation, either version 2 of that License or (at your option) any
0021 * later version.
0022 *
0023 * This software is provided by Freescale Semiconductor "as is" and any
0024 * express or implied warranties, including, but not limited to, the implied
0025 * warranties of merchantability and fitness for a particular purpose are
0026 * disclaimed. In no event shall Freescale Semiconductor be liable for any
0027 * direct, indirect, incidental, special, exemplary, or consequential damages
0028 * (including, but not limited to, procurement of substitute goods or services;
0029 * loss of use, data, or profits; or business interruption) however caused and
0030 * on any theory of liability, whether in contract, strict liability, or tort
0031 * (including negligence or otherwise) arising in any way out of the use of
0032 * this software, even if advised of the possibility of such damage.
0033 */
0034
0035 /dts-v1/;
0036
0037 /include/ "e6500_power_isa.dtsi"
0038
0039 / {
0040 compatible = "fsl,B4420";
0041 #address-cells = <2>;
0042 #size-cells = <2>;
0043 interrupt-parent = <&mpic>;
0044
0045 aliases {
0046 ccsr = &soc;
0047 dcsr = &dcsr;
0048
0049 serial0 = &serial0;
0050 serial1 = &serial1;
0051 serial2 = &serial2;
0052 serial3 = &serial3;
0053 pci0 = &pci0;
0054 usb0 = &usb0;
0055 dma0 = &dma0;
0056 dma1 = &dma1;
0057 sdhc = &sdhc;
0058
0059 fman0 = &fman0;
0060 ethernet0 = &enet0;
0061 ethernet1 = &enet1;
0062 ethernet2 = &enet2;
0063 ethernet3 = &enet3;
0064 };
0065
0066 cpus {
0067 #address-cells = <1>;
0068 #size-cells = <0>;
0069
0070 cpu0: PowerPC,e6500@0 {
0071 device_type = "cpu";
0072 reg = <0 1>;
0073 clocks = <&clockgen 1 0>;
0074 next-level-cache = <&L2_1>;
0075 fsl,portid-mapping = <0x80000000>;
0076 };
0077 cpu1: PowerPC,e6500@2 {
0078 device_type = "cpu";
0079 reg = <2 3>;
0080 clocks = <&clockgen 1 0>;
0081 next-level-cache = <&L2_1>;
0082 fsl,portid-mapping = <0x80000000>;
0083 };
0084 };
0085 };
