0001 /*
0002 * Device Tree Source for IBM Embedded PPC 476 Platform
0003 *
0004 * Copyright © 2011 Tony Breeds IBM Corporation
0005 *
0006 * This file is licensed under the terms of the GNU General Public
0007 * License version 2. This program is licensed "as is" without
0008 * any warranty of any kind, whether express or implied.
0009 */
0010
0011 /dts-v1/;
0012
0013 /memreserve/ 0x01f00000 0x00100000; // spin table
0014
0015 / {
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018 model = "ibm,currituck";
0019 compatible = "ibm,currituck";
0020 dcr-parent = <&{/cpus/cpu@0}>;
0021
0022 aliases {
0023 serial0 = &UART0;
0024 };
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 cpu@0 {
0031 device_type = "cpu";
0032 model = "PowerPC,476";
0033 reg = <0>;
0034 clock-frequency = <1600000000>; // 1.6 GHz
0035 timebase-frequency = <100000000>; // 100Mhz
0036 i-cache-line-size = <32>;
0037 d-cache-line-size = <32>;
0038 i-cache-size = <32768>;
0039 d-cache-size = <32768>;
0040 dcr-controller;
0041 dcr-access-method = "native";
0042 status = "okay";
0043 };
0044 cpu@1 {
0045 device_type = "cpu";
0046 model = "PowerPC,476";
0047 reg = <1>;
0048 clock-frequency = <1600000000>; // 1.6 GHz
0049 timebase-frequency = <100000000>; // 100Mhz
0050 i-cache-line-size = <32>;
0051 d-cache-line-size = <32>;
0052 i-cache-size = <32768>;
0053 d-cache-size = <32768>;
0054 dcr-controller;
0055 dcr-access-method = "native";
0056 status = "disabled";
0057 enable-method = "spin-table";
0058 cpu-release-addr = <0x0 0x01f00000>;
0059 };
0060 };
0061
0062 memory {
0063 device_type = "memory";
0064 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
0065 };
0066
0067 MPIC: interrupt-controller {
0068 compatible = "chrp,open-pic";
0069 interrupt-controller;
0070 dcr-reg = <0xffc00000 0x00040000>;
0071 #address-cells = <0>;
0072 #size-cells = <0>;
0073 #interrupt-cells = <2>;
0074
0075 };
0076
0077 plb {
0078 compatible = "ibm,plb6";
0079 #address-cells = <2>;
0080 #size-cells = <2>;
0081 ranges;
0082 clock-frequency = <200000000>; // 200Mhz
0083
0084 POB0: opb {
0085 compatible = "ibm,opb-4xx", "ibm,opb";
0086 #address-cells = <1>;
0087 #size-cells = <1>;
0088 /* Wish there was a nicer way of specifying a full
0089 * 32-bit range
0090 */
0091 ranges = <0x00000000 0x00000200 0x00000000 0x80000000
0092 0x80000000 0x00000200 0x80000000 0x80000000>;
0093 clock-frequency = <100000000>;
0094
0095 UART0: serial@10000000 {
0096 device_type = "serial";
0097 compatible = "ns16750", "ns16550";
0098 reg = <0x10000000 0x00000008>;
0099 virtual-reg = <0xe1000000>;
0100 clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
0101 current-speed = <115200>;
0102 interrupt-parent = <&MPIC>;
0103 interrupts = <34 2>;
0104 };
0105
0106 FPGA0: fpga@50000000 {
0107 compatible = "ibm,currituck-fpga";
0108 reg = <0x50000000 0x4>;
0109 };
0110
0111 IIC0: i2c@0 {
0112 compatible = "ibm,iic-currituck", "ibm,iic";
0113 reg = <0x0 0x00000014>;
0114 interrupt-parent = <&MPIC>;
0115 interrupts = <79 2>;
0116 #address-cells = <1>;
0117 #size-cells = <0>;
0118 rtc@68 {
0119 compatible = "st,m41t80", "m41st85";
0120 reg = <0x68>;
0121 };
0122 };
0123 };
0124
0125 PCIE0: pcie@10100000000 { // 4xGBIF1
0126 device_type = "pci";
0127 #interrupt-cells = <1>;
0128 #size-cells = <2>;
0129 #address-cells = <3>;
0130 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
0131 primary;
0132 port = <0x0>; /* port number */
0133 reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
0134 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
0135 dcr-reg = <0x80 0x20>;
0136
0137 // pci_space < pci_addr > < cpu_addr > < size >
0138 ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
0139 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
0140
0141 /* Inbound starting at 0 to memsize filled in by zImage */
0142 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
0143
0144 /* This drives busses 0 to 0xf */
0145 bus-range = <0x0 0xf>;
0146
0147 /* Legacy interrupts (note the weird polarity, the bridge seems
0148 * to invert PCIe legacy interrupts).
0149 * We are de-swizzling here because the numbers are actually for
0150 * port of the root complex virtual P2P bridge. But I want
0151 * to avoid putting a node for it in the tree, so the numbers
0152 * below are basically de-swizzled numbers.
0153 * The real slot is on idsel 0, so the swizzling is 1:1
0154 */
0155 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0156 interrupt-map = <
0157 0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
0158 0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
0159 0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
0160 0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
0161 };
0162
0163 PCIE1: pcie@30100000000 { // 4xGBIF0
0164 device_type = "pci";
0165 #interrupt-cells = <1>;
0166 #size-cells = <2>;
0167 #address-cells = <3>;
0168 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
0169 primary;
0170 port = <0x1>; /* port number */
0171 reg = <0x00000301 0x00000000 0x0 0x10000000 /* Config space access */
0172 0x00000300 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
0173 dcr-reg = <0x60 0x20>;
0174
0175 ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
0176 0x01000000 0x0 0x0 0x00000340 0x0 0x0 0x00010000>;
0177
0178 /* Inbound starting at 0 to memsize filled in by zImage */
0179 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
0180
0181 /* This drives busses 0 to 0xf */
0182 bus-range = <0x0 0xf>;
0183
0184 /* Legacy interrupts (note the weird polarity, the bridge seems
0185 * to invert PCIe legacy interrupts).
0186 * We are de-swizzling here because the numbers are actually for
0187 * port of the root complex virtual P2P bridge. But I want
0188 * to avoid putting a node for it in the tree, so the numbers
0189 * below are basically de-swizzled numbers.
0190 * The real slot is on idsel 0, so the swizzling is 1:1
0191 */
0192 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0193 interrupt-map = <
0194 0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
0195 0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
0196 0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
0197 0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
0198 };
0199
0200 PCIE2: pcie@38100000000 { // 2xGBIF0
0201 device_type = "pci";
0202 #interrupt-cells = <1>;
0203 #size-cells = <2>;
0204 #address-cells = <3>;
0205 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
0206 primary;
0207 port = <0x2>; /* port number */
0208 reg = <0x00000381 0x00000000 0x0 0x10000000 /* Config space access */
0209 0x00000380 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
0210 dcr-reg = <0xA0 0x20>;
0211
0212 ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
0213 0x01000000 0x0 0x0 0x000003C0 0x0 0x0 0x00010000>;
0214
0215 /* Inbound starting at 0 to memsize filled in by zImage */
0216 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
0217
0218 /* This drives busses 0 to 0xf */
0219 bus-range = <0x0 0xf>;
0220
0221 /* Legacy interrupts (note the weird polarity, the bridge seems
0222 * to invert PCIe legacy interrupts).
0223 * We are de-swizzling here because the numbers are actually for
0224 * port of the root complex virtual P2P bridge. But I want
0225 * to avoid putting a node for it in the tree, so the numbers
0226 * below are basically de-swizzled numbers.
0227 * The real slot is on idsel 0, so the swizzling is 1:1
0228 */
0229 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0230 interrupt-map = <
0231 0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
0232 0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
0233 0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
0234 0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
0235 };
0236
0237 };
0238
0239 chosen {
0240 stdout-path = &UART0;
0241 };
0242 };
