0001 /*
0002 * Device Tree Source for AMCC Canyonlands (460EX)
0003 *
0004 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
0005 *
0006 * This file is licensed under the terms of the GNU General Public
0007 * License version 2. This program is licensed "as is" without
0008 * any warranty of any kind, whether express or implied.
0009 */
0010
0011 /dts-v1/;
0012
0013 / {
0014 #address-cells = <2>;
0015 #size-cells = <1>;
0016 model = "amcc,canyonlands";
0017 compatible = "amcc,canyonlands";
0018 dcr-parent = <&{/cpus/cpu@0}>;
0019
0020 aliases {
0021 ethernet0 = &EMAC0;
0022 ethernet1 = &EMAC1;
0023 serial0 = &UART0;
0024 serial1 = &UART1;
0025 };
0026
0027 cpus {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030
0031 cpu@0 {
0032 device_type = "cpu";
0033 model = "PowerPC,460EX";
0034 reg = <0x00000000>;
0035 clock-frequency = <0>; /* Filled in by U-Boot */
0036 timebase-frequency = <0>; /* Filled in by U-Boot */
0037 i-cache-line-size = <32>;
0038 d-cache-line-size = <32>;
0039 i-cache-size = <32768>;
0040 d-cache-size = <32768>;
0041 dcr-controller;
0042 dcr-access-method = "native";
0043 next-level-cache = <&L2C0>;
0044 };
0045 };
0046
0047 memory {
0048 device_type = "memory";
0049 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
0050 };
0051
0052 UIC0: interrupt-controller0 {
0053 compatible = "ibm,uic-460ex","ibm,uic";
0054 interrupt-controller;
0055 cell-index = <0>;
0056 dcr-reg = <0x0c0 0x009>;
0057 #address-cells = <0>;
0058 #size-cells = <0>;
0059 #interrupt-cells = <2>;
0060 };
0061
0062 UIC1: interrupt-controller1 {
0063 compatible = "ibm,uic-460ex","ibm,uic";
0064 interrupt-controller;
0065 cell-index = <1>;
0066 dcr-reg = <0x0d0 0x009>;
0067 #address-cells = <0>;
0068 #size-cells = <0>;
0069 #interrupt-cells = <2>;
0070 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
0071 interrupt-parent = <&UIC0>;
0072 };
0073
0074 UIC2: interrupt-controller2 {
0075 compatible = "ibm,uic-460ex","ibm,uic";
0076 interrupt-controller;
0077 cell-index = <2>;
0078 dcr-reg = <0x0e0 0x009>;
0079 #address-cells = <0>;
0080 #size-cells = <0>;
0081 #interrupt-cells = <2>;
0082 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
0083 interrupt-parent = <&UIC0>;
0084 };
0085
0086 UIC3: interrupt-controller3 {
0087 compatible = "ibm,uic-460ex","ibm,uic";
0088 interrupt-controller;
0089 cell-index = <3>;
0090 dcr-reg = <0x0f0 0x009>;
0091 #address-cells = <0>;
0092 #size-cells = <0>;
0093 #interrupt-cells = <2>;
0094 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
0095 interrupt-parent = <&UIC0>;
0096 };
0097
0098 SDR0: sdr {
0099 compatible = "ibm,sdr-460ex";
0100 dcr-reg = <0x00e 0x002>;
0101 };
0102
0103 CPR0: cpr {
0104 compatible = "ibm,cpr-460ex";
0105 dcr-reg = <0x00c 0x002>;
0106 };
0107
0108 CPM0: cpm {
0109 compatible = "ibm,cpm";
0110 dcr-access-method = "native";
0111 dcr-reg = <0x160 0x003>;
0112 unused-units = <0x00000100>;
0113 idle-doze = <0x02000000>;
0114 standby = <0xfeff791d>;
0115 };
0116
0117 L2C0: l2c {
0118 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
0119 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
0120 0x030 0x008>; /* L2 cache DCR's */
0121 cache-line-size = <32>; /* 32 bytes */
0122 cache-size = <262144>; /* L2, 256K */
0123 interrupt-parent = <&UIC1>;
0124 interrupts = <11 1>;
0125 };
0126
0127 plb {
0128 compatible = "ibm,plb-460ex", "ibm,plb4";
0129 #address-cells = <2>;
0130 #size-cells = <1>;
0131 ranges;
0132 clock-frequency = <0>; /* Filled in by U-Boot */
0133
0134 SDRAM0: sdram {
0135 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
0136 dcr-reg = <0x010 0x002>;
0137 };
0138
0139 CRYPTO: crypto@180000 {
0140 compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
0141 reg = <4 0x00180000 0x80400>;
0142 interrupt-parent = <&UIC0>;
0143 interrupts = <0x1d 0x4>;
0144 };
0145
0146 HWRNG: hwrng@110000 {
0147 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
0148 reg = <4 0x00110000 0x50>;
0149 };
0150
0151 MAL0: mcmal {
0152 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
0153 dcr-reg = <0x180 0x062>;
0154 num-tx-chans = <2>;
0155 num-rx-chans = <16>;
0156 #address-cells = <0>;
0157 #size-cells = <0>;
0158 interrupt-parent = <&UIC2>;
0159 interrupts = < /*TXEOB*/ 0x6 0x4
0160 /*RXEOB*/ 0x7 0x4
0161 /*SERR*/ 0x3 0x4
0162 /*TXDE*/ 0x4 0x4
0163 /*RXDE*/ 0x5 0x4>;
0164 };
0165
0166 USB0: ehci@bffd0400 {
0167 compatible = "ibm,usb-ehci-460ex", "usb-ehci";
0168 interrupt-parent = <&UIC2>;
0169 interrupts = <0x1d 4>;
0170 reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
0171 };
0172
0173 USB1: usb@bffd0000 {
0174 compatible = "ohci-le";
0175 reg = <4 0xbffd0000 0x60>;
0176 interrupt-parent = <&UIC2>;
0177 interrupts = <0x1e 4>;
0178 };
0179
0180 USBOTG0: usbotg@bff80000 {
0181 compatible = "amcc,dwc-otg";
0182 reg = <0x4 0xbff80000 0x10000>;
0183 interrupt-parent = <&USBOTG0>;
0184 #interrupt-cells = <1>;
0185 #address-cells = <0>;
0186 #size-cells = <0>;
0187 interrupts = <0x0 0x1 0x2>;
0188 interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
0189 /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
0190 /* DMA */ 0x2 &UIC0 0xc 0x4>;
0191 };
0192
0193 AHBDMA: dma@bffd0800 {
0194 compatible = "snps,dma-spear1340";
0195 reg = <4 0xbffd0800 0x400>;
0196 interrupt-parent = <&UIC3>;
0197 interrupts = <0x5 0x4>;
0198 #dma-cells = <3>;
0199 };
0200
0201 SATA0: sata@bffd1000 {
0202 compatible = "amcc,sata-460ex";
0203 reg = <4 0xbffd1000 0x800>;
0204 interrupt-parent = <&UIC3>;
0205 interrupts = <0x0 0x4>;
0206 dmas = <&AHBDMA 0 1 0>;
0207 dma-names = "sata-dma";
0208 };
0209
0210 POB0: opb {
0211 compatible = "ibm,opb-460ex", "ibm,opb";
0212 #address-cells = <1>;
0213 #size-cells = <1>;
0214 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
0215 clock-frequency = <0>; /* Filled in by U-Boot */
0216
0217 EBC0: ebc {
0218 compatible = "ibm,ebc-460ex", "ibm,ebc";
0219 dcr-reg = <0x012 0x002>;
0220 #address-cells = <2>;
0221 #size-cells = <1>;
0222 clock-frequency = <0>; /* Filled in by U-Boot */
0223 /* ranges property is supplied by U-Boot */
0224 interrupts = <0x6 0x4>;
0225 interrupt-parent = <&UIC1>;
0226
0227 nor_flash@0,0 {
0228 compatible = "amd,s29gl512n", "cfi-flash";
0229 bank-width = <2>;
0230 reg = <0x00000000 0x00000000 0x04000000>;
0231 #address-cells = <1>;
0232 #size-cells = <1>;
0233 partition@0 {
0234 label = "kernel";
0235 reg = <0x00000000 0x001e0000>;
0236 };
0237 partition@1e0000 {
0238 label = "dtb";
0239 reg = <0x001e0000 0x00020000>;
0240 };
0241 partition@200000 {
0242 label = "ramdisk";
0243 reg = <0x00200000 0x01400000>;
0244 };
0245 partition@1600000 {
0246 label = "jffs2";
0247 reg = <0x01600000 0x00400000>;
0248 };
0249 partition@1a00000 {
0250 label = "user";
0251 reg = <0x01a00000 0x02560000>;
0252 };
0253 partition@3f60000 {
0254 label = "env";
0255 reg = <0x03f60000 0x00040000>;
0256 };
0257 partition@3fa0000 {
0258 label = "u-boot";
0259 reg = <0x03fa0000 0x00060000>;
0260 };
0261 };
0262
0263 cpld@2,0 {
0264 compatible = "amcc,ppc460ex-bcsr";
0265 reg = <2 0x0 0x9>;
0266 };
0267
0268 ndfc@3,0 {
0269 compatible = "ibm,ndfc";
0270 reg = <0x00000003 0x00000000 0x00002000>;
0271 ccr = <0x00001000>;
0272 bank-settings = <0x80002222>;
0273 #address-cells = <1>;
0274 #size-cells = <1>;
0275
0276 nand {
0277 #address-cells = <1>;
0278 #size-cells = <1>;
0279
0280 partition@0 {
0281 label = "u-boot";
0282 reg = <0x00000000 0x00100000>;
0283 };
0284 partition@100000 {
0285 label = "user";
0286 reg = <0x00000000 0x03f00000>;
0287 };
0288 };
0289 };
0290 };
0291
0292 UART0: serial@ef600300 {
0293 device_type = "serial";
0294 compatible = "ns16550";
0295 reg = <0xef600300 0x00000008>;
0296 virtual-reg = <0xef600300>;
0297 clock-frequency = <0>; /* Filled in by U-Boot */
0298 current-speed = <0>; /* Filled in by U-Boot */
0299 interrupt-parent = <&UIC1>;
0300 interrupts = <0x1 0x4>;
0301 };
0302
0303 UART1: serial@ef600400 {
0304 device_type = "serial";
0305 compatible = "ns16550";
0306 reg = <0xef600400 0x00000008>;
0307 virtual-reg = <0xef600400>;
0308 clock-frequency = <0>; /* Filled in by U-Boot */
0309 current-speed = <0>; /* Filled in by U-Boot */
0310 interrupt-parent = <&UIC0>;
0311 interrupts = <0x1 0x4>;
0312 };
0313
0314 IIC0: i2c@ef600700 {
0315 compatible = "ibm,iic-460ex", "ibm,iic";
0316 reg = <0xef600700 0x00000014>;
0317 interrupt-parent = <&UIC0>;
0318 interrupts = <0x2 0x4>;
0319 #address-cells = <1>;
0320 #size-cells = <0>;
0321 rtc@68 {
0322 compatible = "st,m41t80";
0323 reg = <0x68>;
0324 interrupt-parent = <&UIC2>;
0325 interrupts = <0x19 0x8>;
0326 };
0327 sttm@48 {
0328 compatible = "ad,ad7414";
0329 reg = <0x48>;
0330 interrupt-parent = <&UIC1>;
0331 interrupts = <0x14 0x8>;
0332 };
0333 };
0334
0335 IIC1: i2c@ef600800 {
0336 compatible = "ibm,iic-460ex", "ibm,iic";
0337 reg = <0xef600800 0x00000014>;
0338 interrupt-parent = <&UIC0>;
0339 interrupts = <0x3 0x4>;
0340 };
0341
0342 GPIO0: gpio@ef600b00 {
0343 compatible = "ibm,ppc4xx-gpio";
0344 reg = <0xef600b00 0x00000048>;
0345 gpio-controller;
0346 };
0347
0348 ZMII0: emac-zmii@ef600d00 {
0349 compatible = "ibm,zmii-460ex", "ibm,zmii";
0350 reg = <0xef600d00 0x0000000c>;
0351 };
0352
0353 RGMII0: emac-rgmii@ef601500 {
0354 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
0355 reg = <0xef601500 0x00000008>;
0356 has-mdio;
0357 };
0358
0359 TAH0: emac-tah@ef601350 {
0360 compatible = "ibm,tah-460ex", "ibm,tah";
0361 reg = <0xef601350 0x00000030>;
0362 };
0363
0364 TAH1: emac-tah@ef601450 {
0365 compatible = "ibm,tah-460ex", "ibm,tah";
0366 reg = <0xef601450 0x00000030>;
0367 };
0368
0369 EMAC0: ethernet@ef600e00 {
0370 device_type = "network";
0371 compatible = "ibm,emac-460ex", "ibm,emac4sync";
0372 interrupt-parent = <&EMAC0>;
0373 interrupts = <0x0 0x1>;
0374 #interrupt-cells = <1>;
0375 #address-cells = <0>;
0376 #size-cells = <0>;
0377 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
0378 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
0379 reg = <0xef600e00 0x000000c4>;
0380 local-mac-address = [000000000000]; /* Filled in by U-Boot */
0381 mal-device = <&MAL0>;
0382 mal-tx-channel = <0>;
0383 mal-rx-channel = <0>;
0384 cell-index = <0>;
0385 max-frame-size = <9000>;
0386 rx-fifo-size = <4096>;
0387 tx-fifo-size = <2048>;
0388 rx-fifo-size-gige = <16384>;
0389 phy-mode = "rgmii";
0390 phy-map = <0x00000000>;
0391 rgmii-device = <&RGMII0>;
0392 rgmii-channel = <0>;
0393 tah-device = <&TAH0>;
0394 tah-channel = <0>;
0395 has-inverted-stacr-oc;
0396 has-new-stacr-staopc;
0397 };
0398
0399 EMAC1: ethernet@ef600f00 {
0400 device_type = "network";
0401 compatible = "ibm,emac-460ex", "ibm,emac4sync";
0402 interrupt-parent = <&EMAC1>;
0403 interrupts = <0x0 0x1>;
0404 #interrupt-cells = <1>;
0405 #address-cells = <0>;
0406 #size-cells = <0>;
0407 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
0408 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
0409 reg = <0xef600f00 0x000000c4>;
0410 local-mac-address = [000000000000]; /* Filled in by U-Boot */
0411 mal-device = <&MAL0>;
0412 mal-tx-channel = <1>;
0413 mal-rx-channel = <8>;
0414 cell-index = <1>;
0415 max-frame-size = <9000>;
0416 rx-fifo-size = <4096>;
0417 tx-fifo-size = <2048>;
0418 rx-fifo-size-gige = <16384>;
0419 phy-mode = "rgmii";
0420 phy-map = <0x00000000>;
0421 rgmii-device = <&RGMII0>;
0422 rgmii-channel = <1>;
0423 tah-device = <&TAH1>;
0424 tah-channel = <1>;
0425 has-inverted-stacr-oc;
0426 has-new-stacr-staopc;
0427 mdio-device = <&EMAC0>;
0428 };
0429 };
0430
0431 PCIX0: pci@c0ec00000 {
0432 device_type = "pci";
0433 #interrupt-cells = <1>;
0434 #size-cells = <2>;
0435 #address-cells = <3>;
0436 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
0437 primary;
0438 large-inbound-windows;
0439 enable-msi-hole;
0440 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
0441 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
0442 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
0443 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
0444 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
0445
0446 /* Outbound ranges, one memory and one IO,
0447 * later cannot be changed
0448 */
0449 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
0450 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
0451 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
0452
0453 /* Inbound 2GB range starting at 0 */
0454 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
0455
0456 /* This drives busses 0 to 0x3f */
0457 bus-range = <0x0 0x3f>;
0458
0459 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
0460 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
0461 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
0462 };
0463
0464 PCIE0: pcie@d00000000 {
0465 device_type = "pci";
0466 #interrupt-cells = <1>;
0467 #size-cells = <2>;
0468 #address-cells = <3>;
0469 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
0470 primary;
0471 port = <0x0>; /* port number */
0472 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
0473 0x0000000c 0x08010000 0x00001000>; /* Registers */
0474 dcr-reg = <0x100 0x020>;
0475 sdr-base = <0x300>;
0476
0477 /* Outbound ranges, one memory and one IO,
0478 * later cannot be changed
0479 */
0480 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
0481 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
0482 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
0483
0484 /* Inbound 2GB range starting at 0 */
0485 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
0486
0487 /* This drives busses 40 to 0x7f */
0488 bus-range = <0x40 0x7f>;
0489
0490 /* Legacy interrupts (note the weird polarity, the bridge seems
0491 * to invert PCIe legacy interrupts).
0492 * We are de-swizzling here because the numbers are actually for
0493 * port of the root complex virtual P2P bridge. But I want
0494 * to avoid putting a node for it in the tree, so the numbers
0495 * below are basically de-swizzled numbers.
0496 * The real slot is on idsel 0, so the swizzling is 1:1
0497 */
0498 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0499 interrupt-map = <
0500 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
0501 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
0502 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
0503 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
0504 };
0505
0506 PCIE1: pcie@d20000000 {
0507 device_type = "pci";
0508 #interrupt-cells = <1>;
0509 #size-cells = <2>;
0510 #address-cells = <3>;
0511 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
0512 primary;
0513 port = <0x1>; /* port number */
0514 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
0515 0x0000000c 0x08011000 0x00001000>; /* Registers */
0516 dcr-reg = <0x120 0x020>;
0517 sdr-base = <0x340>;
0518
0519 /* Outbound ranges, one memory and one IO,
0520 * later cannot be changed
0521 */
0522 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
0523 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
0524 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
0525
0526 /* Inbound 2GB range starting at 0 */
0527 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
0528
0529 /* This drives busses 80 to 0xbf */
0530 bus-range = <0x80 0xbf>;
0531
0532 /* Legacy interrupts (note the weird polarity, the bridge seems
0533 * to invert PCIe legacy interrupts).
0534 * We are de-swizzling here because the numbers are actually for
0535 * port of the root complex virtual P2P bridge. But I want
0536 * to avoid putting a node for it in the tree, so the numbers
0537 * below are basically de-swizzled numbers.
0538 * The real slot is on idsel 0, so the swizzling is 1:1
0539 */
0540 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0541 interrupt-map = <
0542 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
0543 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
0544 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
0545 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
0546 };
0547 };
0548 };
