0001 /*
0002 * Device Tree Source for IBM Embedded PPC 476 Platform
0003 *
0004 * Copyright © 2013 Tony Breeds IBM Corporation
0005 * Copyright © 2013 Alistair Popple IBM Corporation
0006 *
0007 * This file is licensed under the terms of the GNU General Public
0008 * License version 2. This program is licensed "as is" without
0009 * any warranty of any kind, whether express or implied.
0010 */
0011
0012 /dts-v1/;
0013
0014 /memreserve/ 0x01f00000 0x00100000; // spin table
0015
0016 / {
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019 model = "ibm,akebono";
0020 compatible = "ibm,akebono", "ibm,476gtr";
0021 dcr-parent = <&{/cpus/cpu@0}>;
0022
0023 aliases {
0024 serial0 = &UART0;
0025 };
0026
0027 cpus {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030
0031 cpu@0 {
0032 device_type = "cpu";
0033 model = "PowerPC,476";
0034 reg = <0>;
0035 clock-frequency = <1600000000>; // 1.6 GHz
0036 timebase-frequency = <100000000>; // 100Mhz
0037 i-cache-line-size = <32>;
0038 d-cache-line-size = <32>;
0039 i-cache-size = <32768>;
0040 d-cache-size = <32768>;
0041 dcr-controller;
0042 dcr-access-method = "native";
0043 status = "okay";
0044 };
0045 cpu@1 {
0046 device_type = "cpu";
0047 model = "PowerPC,476";
0048 reg = <1>;
0049 clock-frequency = <1600000000>; // 1.6 GHz
0050 timebase-frequency = <100000000>; // 100Mhz
0051 i-cache-line-size = <32>;
0052 d-cache-line-size = <32>;
0053 i-cache-size = <32768>;
0054 d-cache-size = <32768>;
0055 dcr-controller;
0056 dcr-access-method = "native";
0057 status = "disabled";
0058 enable-method = "spin-table";
0059 cpu-release-addr = <0x0 0x01f00000>;
0060 };
0061 };
0062
0063 memory {
0064 device_type = "memory";
0065 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
0066 };
0067
0068 MPIC: interrupt-controller {
0069 compatible = "chrp,open-pic";
0070 interrupt-controller;
0071 dcr-reg = <0xffc00000 0x00040000>;
0072 #address-cells = <0>;
0073 #size-cells = <0>;
0074 #interrupt-cells = <2>;
0075 single-cpu-affinity;
0076 };
0077
0078 plb {
0079 compatible = "ibm,plb6";
0080 #address-cells = <2>;
0081 #size-cells = <2>;
0082 ranges;
0083 clock-frequency = <200000000>; // 200Mhz
0084
0085 HSTA0: hsta@310000e0000 {
0086 compatible = "ibm,476gtr-hsta-msi", "ibm,hsta-msi";
0087 reg = <0x310 0x000e0000 0x0 0xf0>;
0088 interrupt-parent = <&MPIC>;
0089 interrupts = <108 0
0090 109 0
0091 110 0
0092 111 0
0093 112 0
0094 113 0
0095 114 0
0096 115 0
0097 116 0
0098 117 0
0099 118 0
0100 119 0
0101 120 0
0102 121 0
0103 122 0
0104 123 0>;
0105 };
0106
0107 MAL0: mcmal {
0108 compatible = "ibm,mcmal-476gtr", "ibm,mcmal2";
0109 dcr-reg = <0xc0000000 0x062>;
0110 num-tx-chans = <1>;
0111 num-rx-chans = <1>;
0112 #address-cells = <0>;
0113 #size-cells = <0>;
0114 interrupt-parent = <&MPIC>;
0115 interrupts = < /*TXEOB*/ 77 0x4
0116 /*RXEOB*/ 78 0x4
0117 /*SERR*/ 76 0x4
0118 /*TXDE*/ 79 0x4
0119 /*RXDE*/ 80 0x4>;
0120 };
0121
0122 SATA0: sata@30000010000 {
0123 compatible = "ibm,476gtr-ahci";
0124 reg = <0x300 0x00010000 0x0 0x10000>;
0125 interrupt-parent = <&MPIC>;
0126 interrupts = <93 2>;
0127 };
0128
0129 EHCI0: ehci@30010000000 {
0130 compatible = "ibm,476gtr-ehci", "generic-ehci";
0131 reg = <0x300 0x10000000 0x0 0x10000>;
0132 interrupt-parent = <&MPIC>;
0133 interrupts = <85 2>;
0134 };
0135
0136 SD0: sd@30000000000 {
0137 compatible = "ibm,476gtr-sdhci", "generic-sdhci";
0138 reg = <0x300 0x00000000 0x0 0x10000>;
0139 interrupts = <91 2>;
0140 interrupt-parent = <&MPIC>;
0141 };
0142
0143 OHCI0: ohci@30010010000 {
0144 compatible = "ibm,476gtr-ohci", "generic-ohci";
0145 reg = <0x300 0x10010000 0x0 0x10000>;
0146 interrupt-parent = <&MPIC>;
0147 interrupts = <89 1>;
0148 };
0149
0150 OHCI1: ohci@30010020000 {
0151 compatible = "ibm,476gtr-ohci", "generic-ohci";
0152 reg = <0x300 0x10020000 0x0 0x10000>;
0153 interrupt-parent = <&MPIC>;
0154 interrupts = <88 1>;
0155 };
0156
0157 POB0: opb {
0158 compatible = "ibm,opb-4xx", "ibm,opb";
0159 #address-cells = <1>;
0160 #size-cells = <1>;
0161 /* Wish there was a nicer way of specifying a full
0162 * 32-bit range
0163 */
0164 ranges = <0x00000000 0x0000033f 0x00000000 0x80000000
0165 0x80000000 0x0000033f 0x80000000 0x80000000>;
0166 clock-frequency = <100000000>;
0167
0168 RGMII0: emac-rgmii-wol@50004 {
0169 compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol";
0170 reg = <0x50004 0x00000008>;
0171 has-mdio;
0172 };
0173
0174 EMAC0: ethernet@30000 {
0175 device_type = "network";
0176 compatible = "ibm,emac-476gtr", "ibm,emac4sync";
0177 interrupt-parent = <&EMAC0>;
0178 interrupts = <0x0 0x1>;
0179 #interrupt-cells = <1>;
0180 #address-cells = <0>;
0181 #size-cells = <0>;
0182 interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4
0183 /*Wake*/ 0x1 &MPIC 82 0x4>;
0184 reg = <0x30000 0x78>;
0185
0186 /* local-mac-address will normally be added by
0187 * the wrapper. If your device doesn't support
0188 * passing data to the wrapper (in the form
0189 * local-mac-addr=<hwaddr>) then you will need
0190 * to set it manually here. */
0191 //local-mac-address = [000000000000];
0192
0193 mal-device = <&MAL0>;
0194 mal-tx-channel = <0>;
0195 mal-rx-channel = <0>;
0196 cell-index = <0>;
0197 max-frame-size = <9000>;
0198 rx-fifo-size = <4096>;
0199 tx-fifo-size = <2048>;
0200 rx-fifo-size-gige = <16384>;
0201 phy-mode = "rgmii";
0202 phy-map = <0x00000000>;
0203 rgmii-wol-device = <&RGMII0>;
0204 has-inverted-stacr-oc;
0205 has-new-stacr-staopc;
0206 };
0207
0208 UART0: serial@10000 {
0209 device_type = "serial";
0210 compatible = "ns16750", "ns16550";
0211 reg = <0x10000 0x00000008>;
0212 virtual-reg = <0xe8010000>;
0213 clock-frequency = <1851851>;
0214 current-speed = <38400>;
0215 interrupt-parent = <&MPIC>;
0216 interrupts = <39 2>;
0217 };
0218
0219 IIC0: i2c@0 {
0220 compatible = "ibm,iic-476gtr", "ibm,iic";
0221 reg = <0x0 0x00000020>;
0222 interrupt-parent = <&MPIC>;
0223 interrupts = <37 2>;
0224 #address-cells = <1>;
0225 #size-cells = <0>;
0226 rtc@68 {
0227 compatible = "st,m41t80", "m41st85";
0228 reg = <0x68>;
0229 };
0230 };
0231
0232 IIC1: i2c@100 {
0233 compatible = "ibm,iic-476gtr", "ibm,iic";
0234 reg = <0x100 0x00000020>;
0235 interrupt-parent = <&MPIC>;
0236 interrupts = <38 2>;
0237 #address-cells = <1>;
0238 #size-cells = <0>;
0239 avr@58 {
0240 compatible = "ibm,akebono-avr";
0241 reg = <0x58>;
0242 };
0243 };
0244
0245 FPGA0: fpga@ebc00000 {
0246 compatible = "ibm,akebono-fpga";
0247 reg = <0xebc00000 0x8>;
0248 };
0249 };
0250
0251 PCIE0: pcie@10100000000 {
0252 device_type = "pci";
0253 #interrupt-cells = <1>;
0254 #size-cells = <2>;
0255 #address-cells = <3>;
0256 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
0257 primary;
0258 port = <0x0>; /* port number */
0259 reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
0260 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
0261 dcr-reg = <0xc0 0x20>;
0262
0263 // pci_space < pci_addr > < cpu_addr > < size >
0264 ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
0265 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
0266
0267 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
0268 * PCI devices must be able to write to the HSTA module.
0269 */
0270 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
0271
0272 /* This drives busses 0 to 0xf */
0273 bus-range = <0x0 0xf>;
0274
0275 /* Legacy interrupts (note the weird polarity, the bridge seems
0276 * to invert PCIe legacy interrupts).
0277 * We are de-swizzling here because the numbers are actually for
0278 * port of the root complex virtual P2P bridge. But I want
0279 * to avoid putting a node for it in the tree, so the numbers
0280 * below are basically de-swizzled numbers.
0281 * The real slot is on idsel 0, so the swizzling is 1:1
0282 */
0283 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0284 interrupt-map = <
0285 0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
0286 0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
0287 0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
0288 0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
0289 };
0290
0291 PCIE1: pcie@20100000000 {
0292 device_type = "pci";
0293 #interrupt-cells = <1>;
0294 #size-cells = <2>;
0295 #address-cells = <3>;
0296 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
0297 primary;
0298 port = <0x1>; /* port number */
0299 reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */
0300 0x00000200 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
0301 dcr-reg = <0x100 0x20>;
0302
0303 // pci_space < pci_addr > < cpu_addr > < size >
0304 ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000
0305 0x01000000 0x0 0x0 0x00000240 0x0 0x0 0x00010000>;
0306
0307 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
0308 * PCI devices must be able to write to the HSTA module.
0309 */
0310 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
0311
0312 /* This drives busses 0 to 0xf */
0313 bus-range = <0x0 0xf>;
0314
0315 /* Legacy interrupts (note the weird polarity, the bridge seems
0316 * to invert PCIe legacy interrupts).
0317 * We are de-swizzling here because the numbers are actually for
0318 * port of the root complex virtual P2P bridge. But I want
0319 * to avoid putting a node for it in the tree, so the numbers
0320 * below are basically de-swizzled numbers.
0321 * The real slot is on idsel 0, so the swizzling is 1:1
0322 */
0323 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0324 interrupt-map = <
0325 0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
0326 0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
0327 0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
0328 0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
0329 };
0330
0331 PCIE2: pcie@18100000000 {
0332 device_type = "pci";
0333 #interrupt-cells = <1>;
0334 #size-cells = <2>;
0335 #address-cells = <3>;
0336 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
0337 primary;
0338 port = <0x2>; /* port number */
0339 reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */
0340 0x00000180 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
0341 dcr-reg = <0xe0 0x20>;
0342
0343 // pci_space < pci_addr > < cpu_addr > < size >
0344 ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000
0345 0x01000000 0x0 0x0 0x000001c0 0x0 0x0 0x00010000>;
0346
0347 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
0348 * PCI devices must be able to write to the HSTA module.
0349 */
0350 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
0351
0352 /* This drives busses 0 to 0xf */
0353 bus-range = <0x0 0xf>;
0354
0355 /* Legacy interrupts (note the weird polarity, the bridge seems
0356 * to invert PCIe legacy interrupts).
0357 * We are de-swizzling here because the numbers are actually for
0358 * port of the root complex virtual P2P bridge. But I want
0359 * to avoid putting a node for it in the tree, so the numbers
0360 * below are basically de-swizzled numbers.
0361 * The real slot is on idsel 0, so the swizzling is 1:1
0362 */
0363 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0364 interrupt-map = <
0365 0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
0366 0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
0367 0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
0368 0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
0369 };
0370
0371 PCIE3: pcie@28100000000 {
0372 device_type = "pci";
0373 #interrupt-cells = <1>;
0374 #size-cells = <2>;
0375 #address-cells = <3>;
0376 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
0377 primary;
0378 port = <0x3>; /* port number */
0379 reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */
0380 0x00000280 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
0381 dcr-reg = <0x120 0x20>;
0382
0383 // pci_space < pci_addr > < cpu_addr > < size >
0384 ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000
0385 0x01000000 0x0 0x0 0x000002c0 0x0 0x0 0x00010000>;
0386
0387 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
0388 * PCI devices must be able to write to the HSTA module.
0389 */
0390 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
0391
0392 /* This drives busses 0 to 0xf */
0393 bus-range = <0x0 0xf>;
0394
0395 /* Legacy interrupts (note the weird polarity, the bridge seems
0396 * to invert PCIe legacy interrupts).
0397 * We are de-swizzling here because the numbers are actually for
0398 * port of the root complex virtual P2P bridge. But I want
0399 * to avoid putting a node for it in the tree, so the numbers
0400 * below are basically de-swizzled numbers.
0401 * The real slot is on idsel 0, so the swizzling is 1:1
0402 */
0403 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0404 interrupt-map = <
0405 0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */
0406 0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */
0407 0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */
0408 0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>;
0409 };
0410 };
0411
0412 chosen {
0413 stdout-path = &UART0;
0414 };
0415 };
