0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * a4m072 board Device Tree Source
0004 *
0005 * Copyright (C) 2011 DENX Software Engineering GmbH
0006 * Heiko Schocher <hs@denx.de>
0007 *
0008 * Copyright (C) 2007 Semihalf
0009 * Marian Balakowicz <m8@semihalf.com>
0010 */
0011
0012 /include/ "mpc5200b.dtsi"
0013
0014 &gpt0 { fsl,has-wdt; };
0015 &gpt3 { gpio-controller; };
0016 &gpt4 { gpio-controller; };
0017 &gpt5 { gpio-controller; };
0018
0019 / {
0020 model = "anonymous,a4m072";
0021 compatible = "anonymous,a4m072";
0022
0023 soc5200@f0000000 {
0024 #address-cells = <1>;
0025 #size-cells = <1>;
0026 compatible = "fsl,mpc5200b-immr";
0027 ranges = <0 0xf0000000 0x0000c000>;
0028 reg = <0xf0000000 0x00000100>;
0029 bus-frequency = <0>; /* From boot loader */
0030 system-frequency = <0>; /* From boot loader */
0031
0032 cdm@200 {
0033 fsl,init-ext-48mhz-en = <0x0>;
0034 fsl,init-fd-enable = <0x01>;
0035 fsl,init-fd-counters = <0x3333>;
0036 };
0037
0038 spi@f00 {
0039 status = "disabled";
0040 };
0041
0042 psc@2000 {
0043 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
0044 reg = <0x2000 0x100>;
0045 interrupts = <2 1 0>;
0046 };
0047
0048 psc@2200 {
0049 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
0050 reg = <0x2200 0x100>;
0051 interrupts = <2 2 0>;
0052 };
0053
0054 psc@2400 {
0055 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
0056 reg = <0x2400 0x100>;
0057 interrupts = <2 3 0>;
0058 };
0059
0060 psc@2600 {
0061 status = "disabled";
0062 };
0063
0064 psc@2800 {
0065 status = "disabled";
0066 };
0067
0068 psc@2c00 {
0069 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
0070 reg = <0x2c00 0x100>;
0071 interrupts = <2 4 0>;
0072 };
0073
0074 ethernet@3000 {
0075 phy-handle = <&phy0>;
0076 };
0077
0078 mdio@3000 {
0079 phy0: ethernet-phy@1f {
0080 reg = <0x1f>;
0081 interrupts = <1 2 0>; /* IRQ 2 active low */
0082 };
0083 };
0084
0085 i2c@3d00 {
0086 status = "disabled";
0087 };
0088
0089 i2c@3d40 {
0090 hwmon@2e {
0091 compatible = "nsc,lm87";
0092 reg = <0x2e>;
0093 };
0094 rtc@51 {
0095 compatible = "nxp,rtc8564";
0096 reg = <0x51>;
0097 };
0098 };
0099 };
0100
0101 localbus {
0102 compatible = "fsl,mpc5200b-lpb","simple-bus";
0103 #address-cells = <2>;
0104 #size-cells = <1>;
0105 ranges = <0 0 0xfe000000 0x02000000
0106 1 0 0x62000000 0x00400000
0107 2 0 0x64000000 0x00200000
0108 3 0 0x66000000 0x01000000
0109 6 0 0x68000000 0x01000000
0110 7 0 0x6a000000 0x00000004>;
0111
0112 flash@0,0 {
0113 compatible = "cfi-flash";
0114 reg = <0 0 0x02000000>;
0115 bank-width = <2>;
0116 #size-cells = <1>;
0117 #address-cells = <1>;
0118 };
0119 sram0@1,0 {
0120 compatible = "mtd-ram";
0121 reg = <1 0x00000 0x00400000>;
0122 bank-width = <2>;
0123 };
0124 };
0125
0126 pci@f0000d00 {
0127 #interrupt-cells = <1>;
0128 #size-cells = <2>;
0129 #address-cells = <3>;
0130 device_type = "pci";
0131 compatible = "fsl,mpc5200-pci";
0132 reg = <0xf0000d00 0x100>;
0133 interrupt-map-mask = <0xf800 0 0 7>;
0134 interrupt-map = <
0135 /* IDSEL 0x16 */
0136 0xc000 0 0 1 &mpc5200_pic 1 3 3
0137 0xc000 0 0 2 &mpc5200_pic 1 3 3
0138 0xc000 0 0 3 &mpc5200_pic 1 3 3
0139 0xc000 0 0 4 &mpc5200_pic 1 3 3>;
0140 clock-frequency = <0>; /* From boot loader */
0141 interrupts = <2 8 0 2 9 0 2 10 0>;
0142 bus-range = <0 0>;
0143 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
0144 <0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
0145 <0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
0146 };
0147 };
