txx9/rbtx4927/setup.c

0001 /*
0002  * Toshiba rbtx4927 specific setup
0003  *
0004  * Author: MontaVista Software, Inc.
0005  *     source@mvista.com
0006  *
0007  * Copyright 2001-2002 MontaVista Software Inc.
0008  *
0009  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
0010  * Copyright (C) 2000 RidgeRun, Inc.
0011  * Author: RidgeRun, Inc.
0012  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
0013  *
0014  * Copyright 2001 MontaVista Software Inc.
0015  * Author: jsun@mvista.com or jsun@junsun.net
0016  *
0017  * Copyright 2002 MontaVista Software Inc.
0018  * Author: Michael Pruznick, michael_pruznick@mvista.com
0019  *
0020  * Copyright (C) 2000-2001 Toshiba Corporation
0021  *
0022  * Copyright (C) 2004 MontaVista Software Inc.
0023  * Author: Manish Lachwani, mlachwani@mvista.com
0024  *
0025  *  This program is free software; you can redistribute it and/or modify it
0026  *  under the terms of the GNU General Public License as published by the
0027  *  Free Software Foundation; either version 2 of the License, or (at your
0028  *  option) any later version.
0029  *
0030  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
0031  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0032  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
0033  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
0034  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
0035  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
0036  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0037  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
0038  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
0039  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0040  *
0041  *  You should have received a copy of the GNU General Public License along
0042  *  with this program; if not, write to the Free Software Foundation, Inc.,
0043  *  675 Mass Ave, Cambridge, MA 02139, USA.
0044  */
0045 #include <linux/init.h>
0046 #include <linux/kernel.h>
0047 #include <linux/types.h>
0048 #include <linux/ioport.h>
0049 #include <linux/platform_device.h>
0050 #include <linux/delay.h>
0051 #include <linux/gpio.h>
0052 #include <linux/leds.h>
0053 #include <asm/io.h>
0054 #include <asm/reboot.h>
0055 #include <asm/txx9pio.h>
0056 #include <asm/txx9/generic.h>
0057 #include <asm/txx9/pci.h>
0058 #include <asm/txx9/rbtx4927.h>
0059 #include <asm/txx9/tx4938.h>    /* for TX4937 */
0060
0061 #ifdef CONFIG_PCI
0062 static void __init tx4927_pci_setup(void)
0063 {
0064     int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
0065     struct pci_controller *c = &txx9_primary_pcic;
0066
0067     register_pci_controller(c);
0068
0069     if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
0070         txx9_pci_option =
0071             (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
0072             TXX9_PCI_OPT_CLK_66; /* already configured */
0073
0074     /* Reset PCI Bus */
0075     writeb(1, rbtx4927_pcireset_addr);
0076     /* Reset PCIC */
0077     txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
0078     if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
0079         TXX9_PCI_OPT_CLK_66)
0080         tx4927_pciclk66_setup();
0081     mdelay(10);
0082     /* clear PCIC reset */
0083     txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
0084     writeb(0, rbtx4927_pcireset_addr);
0085     iob();
0086
0087     tx4927_report_pciclk();
0088     tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
0089     if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
0090         TXX9_PCI_OPT_CLK_AUTO &&
0091         txx9_pci66_check(c, 0, 0)) {
0092         /* Reset PCI Bus */
0093         writeb(1, rbtx4927_pcireset_addr);
0094         /* Reset PCIC */
0095         txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
0096         tx4927_pciclk66_setup();
0097         mdelay(10);
0098         /* clear PCIC reset */
0099         txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
0100         writeb(0, rbtx4927_pcireset_addr);
0101         iob();
0102         /* Reinitialize PCIC */
0103         tx4927_report_pciclk();
0104         tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
0105     }
0106     tx4927_setup_pcierr_irq();
0107 }
0108
0109 static void __init tx4937_pci_setup(void)
0110 {
0111     int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
0112     struct pci_controller *c = &txx9_primary_pcic;
0113
0114     register_pci_controller(c);
0115
0116     if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
0117         txx9_pci_option =
0118             (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
0119             TXX9_PCI_OPT_CLK_66; /* already configured */
0120
0121     /* Reset PCI Bus */
0122     writeb(1, rbtx4927_pcireset_addr);
0123     /* Reset PCIC */
0124     txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
0125     if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
0126         TXX9_PCI_OPT_CLK_66)
0127         tx4938_pciclk66_setup();
0128     mdelay(10);
0129     /* clear PCIC reset */
0130     txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
0131     writeb(0, rbtx4927_pcireset_addr);
0132     iob();
0133
0134     tx4938_report_pciclk();
0135     tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
0136     if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
0137         TXX9_PCI_OPT_CLK_AUTO &&
0138         txx9_pci66_check(c, 0, 0)) {
0139         /* Reset PCI Bus */
0140         writeb(1, rbtx4927_pcireset_addr);
0141         /* Reset PCIC */
0142         txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
0143         tx4938_pciclk66_setup();
0144         mdelay(10);
0145         /* clear PCIC reset */
0146         txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
0147         writeb(0, rbtx4927_pcireset_addr);
0148         iob();
0149         /* Reinitialize PCIC */
0150         tx4938_report_pciclk();
0151         tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
0152     }
0153     tx4938_setup_pcierr_irq();
0154 }
0155 #else
0156 static inline void tx4927_pci_setup(void) {}
0157 static inline void tx4937_pci_setup(void) {}
0158 #endif /* CONFIG_PCI */
0159
0160 static void __init rbtx4927_gpio_init(void)
0161 {
0162     /* TX4927-SIO DTR on (PIO[15]) */
0163     gpio_request(15, "sio-dtr");
0164     gpio_direction_output(15, 1);
0165
0166     tx4927_sio_init(0, 0);
0167 }
0168
0169 static void __init rbtx4927_arch_init(void)
0170 {
0171     txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
0172
0173     rbtx4927_gpio_init();
0174
0175     tx4927_pci_setup();
0176 }
0177
0178 static void __init rbtx4937_arch_init(void)
0179 {
0180     txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
0181
0182     rbtx4927_gpio_init();
0183
0184     tx4937_pci_setup();
0185 }
0186
0187 static void toshiba_rbtx4927_restart(char *command)
0188 {
0189     /* enable the s/w reset register */
0190     writeb(1, rbtx4927_softresetlock_addr);
0191
0192     /* wait for enable to be seen */
0193     while (!(readb(rbtx4927_softresetlock_addr) & 1))
0194         ;
0195
0196     /* do a s/w reset */
0197     writeb(1, rbtx4927_softreset_addr);
0198
0199     /* fallback */
0200     (*_machine_halt)();
0201 }
0202
0203 static void __init rbtx4927_clock_init(void);
0204 static void __init rbtx4937_clock_init(void);
0205
0206 static void __init rbtx4927_mem_setup(void)
0207 {
0208     if (TX4927_REV_PCODE() == 0x4927) {
0209         rbtx4927_clock_init();
0210         tx4927_setup();
0211     } else {
0212         rbtx4937_clock_init();
0213         tx4938_setup();
0214     }
0215
0216     _machine_restart = toshiba_rbtx4927_restart;
0217
0218 #ifdef CONFIG_PCI
0219     txx9_alloc_pci_controller(&txx9_primary_pcic,
0220                   RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
0221                   RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
0222     txx9_board_pcibios_setup = tx4927_pcibios_setup;
0223 #else
0224     set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
0225 #endif
0226 }
0227
0228 static void __init rbtx4927_clock_init(void)
0229 {
0230     /*
0231      * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
0232      *
0233      * For TX4927:
0234      * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
0235      * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
0236      * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
0237      * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
0238      * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
0239      * i.e. S9[3]: ON (83MHz), OFF (100MHz)
0240      */
0241     switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
0242         TX4927_CCFG_PCIDIVMODE_MASK) {
0243     case TX4927_CCFG_PCIDIVMODE_2_5:
0244     case TX4927_CCFG_PCIDIVMODE_5:
0245         txx9_cpu_clock = 166666666; /* 166MHz */
0246         break;
0247     default:
0248         txx9_cpu_clock = 200000000; /* 200MHz */
0249     }
0250 }
0251
0252 static void __init rbtx4937_clock_init(void)
0253 {
0254     /*
0255      * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
0256      *
0257      * For TX4937:
0258      * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
0259      * PCIDIVMODE[10] is 0.
0260      * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
0261      * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
0262      * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
0263      * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
0264      * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
0265      * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
0266      */
0267     switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
0268         TX4938_CCFG_PCIDIVMODE_MASK) {
0269     case TX4938_CCFG_PCIDIVMODE_8:
0270     case TX4938_CCFG_PCIDIVMODE_4:
0271         txx9_cpu_clock = 266666666; /* 266MHz */
0272         break;
0273     case TX4938_CCFG_PCIDIVMODE_9:
0274     case TX4938_CCFG_PCIDIVMODE_4_5:
0275         txx9_cpu_clock = 300000000; /* 300MHz */
0276         break;
0277     default:
0278         txx9_cpu_clock = 333333333; /* 333MHz */
0279     }
0280 }
0281
0282 static void __init rbtx4927_time_init(void)
0283 {
0284     tx4927_time_init(0);
0285 }
0286
0287 static void __init toshiba_rbtx4927_rtc_init(void)
0288 {
0289     struct resource res = {
0290         .start  = RBTX4927_BRAMRTC_BASE - IO_BASE,
0291         .end    = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
0292         .flags  = IORESOURCE_MEM,
0293     };
0294     platform_device_register_simple("rtc-ds1742", -1, &res, 1);
0295 }
0296
0297 static void __init rbtx4927_ne_init(void)
0298 {
0299     struct resource res[] = {
0300         {
0301             .start  = RBTX4927_RTL_8019_BASE,
0302             .end    = RBTX4927_RTL_8019_BASE + 0x20 - 1,
0303             .flags  = IORESOURCE_IO,
0304         }, {
0305             .start  = RBTX4927_RTL_8019_IRQ,
0306             .flags  = IORESOURCE_IRQ,
0307         }
0308     };
0309     platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
0310 }
0311
0312 static void __init rbtx4927_mtd_init(void)
0313 {
0314     int i;
0315
0316     for (i = 0; i < 2; i++)
0317         tx4927_mtd_init(i);
0318 }
0319
0320 static void __init rbtx4927_gpioled_init(void)
0321 {
0322     static const struct gpio_led leds[] = {
0323         { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, },
0324         { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, },
0325     };
0326     static struct gpio_led_platform_data pdata = {
0327         .num_leds = ARRAY_SIZE(leds),
0328         .leds = leds,
0329     };
0330     struct platform_device *pdev = platform_device_alloc("leds-gpio", 0);
0331
0332     if (!pdev)
0333         return;
0334     pdev->dev.platform_data = &pdata;
0335     if (platform_device_add(pdev))
0336         platform_device_put(pdev);
0337 }
0338
0339 static void __init rbtx4927_device_init(void)
0340 {
0341     toshiba_rbtx4927_rtc_init();
0342     rbtx4927_ne_init();
0343     tx4927_wdt_init();
0344     rbtx4927_mtd_init();
0345     if (TX4927_REV_PCODE() == 0x4927) {
0346         tx4927_dmac_init(2);
0347         tx4927_aclc_init(0, 1);
0348     } else {
0349         tx4938_dmac_init(0, 2);
0350         tx4938_aclc_init();
0351     }
0352     platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
0353     txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
0354     rbtx4927_gpioled_init();
0355 }
0356
0357 struct txx9_board_vec rbtx4927_vec __initdata = {
0358     .system = "Toshiba RBTX4927",
0359     .prom_init = rbtx4927_prom_init,
0360     .mem_setup = rbtx4927_mem_setup,
0361     .irq_setup = rbtx4927_irq_setup,
0362     .time_init = rbtx4927_time_init,
0363     .device_init = rbtx4927_device_init,
0364     .arch_init = rbtx4927_arch_init,
0365 #ifdef CONFIG_PCI
0366     .pci_map_irq = rbtx4927_pci_map_irq,
0367 #endif
0368 };
0369 struct txx9_board_vec rbtx4937_vec __initdata = {
0370     .system = "Toshiba RBTX4937",
0371     .prom_init = rbtx4927_prom_init,
0372     .mem_setup = rbtx4927_mem_setup,
0373     .irq_setup = rbtx4927_irq_setup,
0374     .time_init = rbtx4927_time_init,
0375     .device_init = rbtx4927_device_init,
0376     .arch_init = rbtx4937_arch_init,
0377 #ifdef CONFIG_PCI
0378     .pci_map_irq = rbtx4927_pci_map_irq,
0379 #endif
0380 };