txx9/generic/setup_tx4927.c

0001 /*
0002  * TX4927 setup routines
0003  * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
0004  *      and RBTX49xx patch from CELF patch archive.
0005  *
0006  * 2003-2005 (c) MontaVista Software, Inc.
0007  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
0008  *
0009  * This file is subject to the terms and conditions of the GNU General Public
0010  * License.  See the file "COPYING" in the main directory of this archive
0011  * for more details.
0012  */
0013 #include <linux/init.h>
0014 #include <linux/ioport.h>
0015 #include <linux/delay.h>
0016 #include <linux/param.h>
0017 #include <linux/ptrace.h>
0018 #include <linux/mtd/physmap.h>
0019 #include <asm/reboot.h>
0020 #include <asm/traps.h>
0021 #include <asm/txx9irq.h>
0022 #include <asm/txx9tmr.h>
0023 #include <asm/txx9pio.h>
0024 #include <asm/txx9/generic.h>
0025 #include <asm/txx9/dmac.h>
0026 #include <asm/txx9/tx4927.h>
0027
0028 static void __init tx4927_wdr_init(void)
0029 {
0030     /* report watchdog reset status */
0031     if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST)
0032         pr_warn("Watchdog reset detected at 0x%lx\n",
0033             read_c0_errorepc());
0034     /* clear WatchDogReset (W1C) */
0035     tx4927_ccfg_set(TX4927_CCFG_WDRST);
0036     /* do reset on watchdog */
0037     tx4927_ccfg_set(TX4927_CCFG_WR);
0038 }
0039
0040 void __init tx4927_wdt_init(void)
0041 {
0042     txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
0043 }
0044
0045 static void tx4927_machine_restart(char *command)
0046 {
0047     local_irq_disable();
0048     pr_emerg("Rebooting (with %s watchdog reset)...\n",
0049          (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) ?
0050          "external" : "internal");
0051     /* clear watchdog status */
0052     tx4927_ccfg_set(TX4927_CCFG_WDRST); /* W1C */
0053     txx9_wdt_now(TX4927_TMR_REG(2) & 0xfffffffffULL);
0054     while (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST))
0055         ;
0056     mdelay(10);
0057     if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) {
0058         pr_emerg("Rebooting (with internal watchdog reset)...\n");
0059         /* External WDRST failed.  Do internal watchdog reset */
0060         tx4927_ccfg_clear(TX4927_CCFG_WDREXEN);
0061     }
0062     /* fallback */
0063     (*_machine_halt)();
0064 }
0065
0066 void show_registers(struct pt_regs *regs);
0067 static int tx4927_be_handler(struct pt_regs *regs, int is_fixup)
0068 {
0069     int data = regs->cp0_cause & 4;
0070     console_verbose();
0071     pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
0072     pr_err("ccfg:%llx, toea:%llx\n",
0073            (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
0074            (unsigned long long)____raw_readq(&tx4927_ccfgptr->toea));
0075 #ifdef CONFIG_PCI
0076     tx4927_report_pcic_status();
0077 #endif
0078     show_registers(regs);
0079     panic("BusError!");
0080 }
0081 static void __init tx4927_be_init(void)
0082 {
0083     mips_set_be_handler(tx4927_be_handler);
0084 }
0085
0086 static struct resource tx4927_sdram_resource[4];
0087
0088 void __init tx4927_setup(void)
0089 {
0090     int i;
0091     __u32 divmode;
0092     unsigned int cpuclk = 0;
0093     u64 ccfg;
0094
0095     txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
0096               TX4927_REG_SIZE);
0097     set_c0_config(TX49_CONF_CWFON);
0098
0099     /* SDRAMC,EBUSC are configured by PROM */
0100     for (i = 0; i < 8; i++) {
0101         if (!(TX4927_EBUSC_CR(i) & 0x8))
0102             continue;   /* disabled */
0103         txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
0104         txx9_ce_res[i].end =
0105             txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
0106         request_resource(&iomem_resource, &txx9_ce_res[i]);
0107     }
0108
0109     /* clocks */
0110     ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
0111     if (txx9_master_clock) {
0112         /* calculate gbus_clock and cpu_clock from master_clock */
0113         divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
0114         switch (divmode) {
0115         case TX4927_CCFG_DIVMODE_8:
0116         case TX4927_CCFG_DIVMODE_10:
0117         case TX4927_CCFG_DIVMODE_12:
0118         case TX4927_CCFG_DIVMODE_16:
0119             txx9_gbus_clock = txx9_master_clock * 4; break;
0120         default:
0121             txx9_gbus_clock = txx9_master_clock;
0122         }
0123         switch (divmode) {
0124         case TX4927_CCFG_DIVMODE_2:
0125         case TX4927_CCFG_DIVMODE_8:
0126             cpuclk = txx9_gbus_clock * 2; break;
0127         case TX4927_CCFG_DIVMODE_2_5:
0128         case TX4927_CCFG_DIVMODE_10:
0129             cpuclk = txx9_gbus_clock * 5 / 2; break;
0130         case TX4927_CCFG_DIVMODE_3:
0131         case TX4927_CCFG_DIVMODE_12:
0132             cpuclk = txx9_gbus_clock * 3; break;
0133         case TX4927_CCFG_DIVMODE_4:
0134         case TX4927_CCFG_DIVMODE_16:
0135             cpuclk = txx9_gbus_clock * 4; break;
0136         }
0137         txx9_cpu_clock = cpuclk;
0138     } else {
0139         if (txx9_cpu_clock == 0)
0140             txx9_cpu_clock = 200000000; /* 200MHz */
0141         /* calculate gbus_clock and master_clock from cpu_clock */
0142         cpuclk = txx9_cpu_clock;
0143         divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
0144         switch (divmode) {
0145         case TX4927_CCFG_DIVMODE_2:
0146         case TX4927_CCFG_DIVMODE_8:
0147             txx9_gbus_clock = cpuclk / 2; break;
0148         case TX4927_CCFG_DIVMODE_2_5:
0149         case TX4927_CCFG_DIVMODE_10:
0150             txx9_gbus_clock = cpuclk * 2 / 5; break;
0151         case TX4927_CCFG_DIVMODE_3:
0152         case TX4927_CCFG_DIVMODE_12:
0153             txx9_gbus_clock = cpuclk / 3; break;
0154         case TX4927_CCFG_DIVMODE_4:
0155         case TX4927_CCFG_DIVMODE_16:
0156             txx9_gbus_clock = cpuclk / 4; break;
0157         }
0158         switch (divmode) {
0159         case TX4927_CCFG_DIVMODE_8:
0160         case TX4927_CCFG_DIVMODE_10:
0161         case TX4927_CCFG_DIVMODE_12:
0162         case TX4927_CCFG_DIVMODE_16:
0163             txx9_master_clock = txx9_gbus_clock / 4; break;
0164         default:
0165             txx9_master_clock = txx9_gbus_clock;
0166         }
0167     }
0168     /* change default value to udelay/mdelay take reasonable time */
0169     loops_per_jiffy = txx9_cpu_clock / HZ / 2;
0170
0171     /* CCFG */
0172     tx4927_wdr_init();
0173     /* clear BusErrorOnWrite flag (W1C) */
0174     tx4927_ccfg_set(TX4927_CCFG_BEOW);
0175     /* enable Timeout BusError */
0176     if (txx9_ccfg_toeon)
0177         tx4927_ccfg_set(TX4927_CCFG_TOE);
0178
0179     /* DMA selection */
0180     txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
0181
0182     /* Use external clock for external arbiter */
0183     if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
0184         txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
0185
0186     pr_info("%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
0187         txx9_pcode_str, (cpuclk + 500000) / 1000000,
0188         (txx9_master_clock + 500000) / 1000000,
0189         (__u32)____raw_readq(&tx4927_ccfgptr->crir),
0190         ____raw_readq(&tx4927_ccfgptr->ccfg),
0191         ____raw_readq(&tx4927_ccfgptr->pcfg));
0192
0193     pr_info("%s SDRAMC --", txx9_pcode_str);
0194     for (i = 0; i < 4; i++) {
0195         __u64 cr = TX4927_SDRAMC_CR(i);
0196         unsigned long base, size;
0197         if (!((__u32)cr & 0x00000400))
0198             continue;   /* disabled */
0199         base = (unsigned long)(cr >> 49) << 21;
0200         size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
0201         pr_cont(" CR%d:%016llx", i, cr);
0202         tx4927_sdram_resource[i].name = "SDRAM";
0203         tx4927_sdram_resource[i].start = base;
0204         tx4927_sdram_resource[i].end = base + size - 1;
0205         tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
0206         request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
0207     }
0208     pr_cont(" TR:%09llx\n", ____raw_readq(&tx4927_sdramcptr->tr));
0209
0210     /* TMR */
0211     /* disable all timers */
0212     for (i = 0; i < TX4927_NR_TMR; i++)
0213         txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
0214
0215     /* PIO */
0216     __raw_writel(0, &tx4927_pioptr->maskcpu);
0217     __raw_writel(0, &tx4927_pioptr->maskext);
0218
0219     _machine_restart = tx4927_machine_restart;
0220     board_be_init = tx4927_be_init;
0221 }
0222
0223 void __init tx4927_time_init(unsigned int tmrnr)
0224 {
0225     if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
0226         txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
0227                      TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
0228                      TXX9_IMCLK);
0229 }
0230
0231 void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
0232 {
0233     int i;
0234
0235     for (i = 0; i < 2; i++)
0236         txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL,
0237                   TXX9_IRQ_BASE + TX4927_IR_SIO(i),
0238                   i, sclk, (1 << i) & cts_mask);
0239 }
0240
0241 void __init tx4927_mtd_init(int ch)
0242 {
0243     struct physmap_flash_data pdata = {
0244         .width = TX4927_EBUSC_WIDTH(ch) / 8,
0245     };
0246     unsigned long start = txx9_ce_res[ch].start;
0247     unsigned long size = txx9_ce_res[ch].end - start + 1;
0248
0249     if (!(TX4927_EBUSC_CR(ch) & 0x8))
0250         return; /* disabled */
0251     txx9_physmap_flash_init(ch, start, size, &pdata);
0252 }
0253
0254 void __init tx4927_dmac_init(int memcpy_chan)
0255 {
0256     struct txx9dmac_platform_data plat_data = {
0257         .memcpy_chan = memcpy_chan,
0258         .have_64bit_regs = true,
0259     };
0260
0261     txx9_dmac_init(0, TX4927_DMA_REG & 0xfffffffffULL,
0262                TXX9_IRQ_BASE + TX4927_IR_DMA(0), &plat_data);
0263 }
0264
0265 void __init tx4927_aclc_init(unsigned int dma_chan_out,
0266                  unsigned int dma_chan_in)
0267 {
0268     u64 pcfg = __raw_readq(&tx4927_ccfgptr->pcfg);
0269     __u64 dmasel_mask = 0, dmasel = 0;
0270     unsigned long flags;
0271
0272     if (!(pcfg & TX4927_PCFG_SEL2))
0273         return;
0274     /* setup DMASEL (playback:ACLC ch0, capture:ACLC ch1) */
0275     switch (dma_chan_out) {
0276     case 0:
0277         dmasel_mask |= TX4927_PCFG_DMASEL0_MASK;
0278         dmasel |= TX4927_PCFG_DMASEL0_ACL0;
0279         break;
0280     case 2:
0281         dmasel_mask |= TX4927_PCFG_DMASEL2_MASK;
0282         dmasel |= TX4927_PCFG_DMASEL2_ACL0;
0283         break;
0284     default:
0285         return;
0286     }
0287     switch (dma_chan_in) {
0288     case 1:
0289         dmasel_mask |= TX4927_PCFG_DMASEL1_MASK;
0290         dmasel |= TX4927_PCFG_DMASEL1_ACL1;
0291         break;
0292     case 3:
0293         dmasel_mask |= TX4927_PCFG_DMASEL3_MASK;
0294         dmasel |= TX4927_PCFG_DMASEL3_ACL1;
0295         break;
0296     default:
0297         return;
0298     }
0299     local_irq_save(flags);
0300     txx9_clear64(&tx4927_ccfgptr->pcfg, dmasel_mask);
0301     txx9_set64(&tx4927_ccfgptr->pcfg, dmasel);
0302     local_irq_restore(flags);
0303     txx9_aclc_init(TX4927_ACLC_REG & 0xfffffffffULL,
0304                TXX9_IRQ_BASE + TX4927_IR_ACLC,
0305                0, dma_chan_out, dma_chan_in);
0306 }
0307
0308 static void __init tx4927_stop_unused_modules(void)
0309 {
0310     __u64 pcfg, rst = 0, ckd = 0;
0311     char buf[128];
0312
0313     buf[0] = '\0';
0314     local_irq_disable();
0315     pcfg = ____raw_readq(&tx4927_ccfgptr->pcfg);
0316     if (!(pcfg & TX4927_PCFG_SEL2)) {
0317         rst |= TX4927_CLKCTR_ACLRST;
0318         ckd |= TX4927_CLKCTR_ACLCKD;
0319         strcat(buf, " ACLC");
0320     }
0321     if (rst | ckd) {
0322         txx9_set64(&tx4927_ccfgptr->clkctr, rst);
0323         txx9_set64(&tx4927_ccfgptr->clkctr, ckd);
0324     }
0325     local_irq_enable();
0326     if (buf[0])
0327         pr_info("%s: stop%s\n", txx9_pcode_str, buf);
0328 }
0329
0330 static int __init tx4927_late_init(void)
0331 {
0332     if (txx9_pcode != 0x4927)
0333         return -ENODEV;
0334     tx4927_stop_unused_modules();
0335     return 0;
0336 }
0337 late_initcall(tx4927_late_init);