txx9/generic/pci.c

0001 /*
0002  * linux/arch/mips/txx9/pci.c
0003  *
0004  * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
0005  *      linux/arch/mips/txx9/rbtx4938/setup.c,
0006  *      and RBTX49xx patch from CELF patch archive.
0007  *
0008  * Copyright 2001-2005 MontaVista Software Inc.
0009  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
0010  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
0011  *
0012  * This file is subject to the terms and conditions of the GNU General Public
0013  * License.  See the file "COPYING" in the main directory of this archive
0014  * for more details.
0015  */
0016 #include <linux/delay.h>
0017 #include <linux/jiffies.h>
0018 #include <linux/io.h>
0019 #include <asm/txx9/generic.h>
0020 #include <asm/txx9/pci.h>
0021 #ifdef CONFIG_TOSHIBA_FPCIB0
0022 #include <linux/interrupt.h>
0023 #include <linux/slab.h>
0024 #include <asm/i8259.h>
0025 #include <asm/txx9/smsc_fdc37m81x.h>
0026 #endif
0027
0028 static int __init
0029 early_read_config_word(struct pci_controller *hose,
0030                int top_bus, int bus, int devfn, int offset, u16 *value)
0031 {
0032     struct pci_bus fake_bus;
0033
0034     fake_bus.number = bus;
0035     fake_bus.sysdata = hose;
0036     fake_bus.ops = hose->pci_ops;
0037
0038     if (bus != top_bus)
0039         /* Fake a parent bus structure. */
0040         fake_bus.parent = &fake_bus;
0041     else
0042         fake_bus.parent = NULL;
0043
0044     return pci_bus_read_config_word(&fake_bus, devfn, offset, value);
0045 }
0046
0047 int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
0048                 int current_bus)
0049 {
0050     u32 pci_devfn;
0051     unsigned short vid;
0052     int cap66 = -1;
0053     u16 stat;
0054
0055     /* It seems SLC90E66 needs some time after PCI reset... */
0056     mdelay(80);
0057
0058     pr_info("PCI: Checking 66MHz capabilities...\n");
0059
0060     for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
0061         if (PCI_FUNC(pci_devfn))
0062             continue;
0063         if (early_read_config_word(hose, top_bus, current_bus,
0064                        pci_devfn, PCI_VENDOR_ID, &vid) !=
0065             PCIBIOS_SUCCESSFUL)
0066             continue;
0067         if (vid == 0xffff)
0068             continue;
0069
0070         /* check 66MHz capability */
0071         if (cap66 < 0)
0072             cap66 = 1;
0073         if (cap66) {
0074             early_read_config_word(hose, top_bus, current_bus,
0075                            pci_devfn, PCI_STATUS, &stat);
0076             if (!(stat & PCI_STATUS_66MHZ)) {
0077                 pr_debug("PCI: %02x:%02x not 66MHz capable.\n",
0078                      current_bus, pci_devfn);
0079                 cap66 = 0;
0080                 break;
0081             }
0082         }
0083     }
0084     return cap66 > 0;
0085 }
0086
0087 static struct resource primary_pci_mem_res[2] = {
0088     { .name = "PCI MEM" },
0089     { .name = "PCI MMIO" },
0090 };
0091 static struct resource primary_pci_io_res = { .name = "PCI IO" };
0092 struct pci_controller txx9_primary_pcic = {
0093     .mem_resource = &primary_pci_mem_res[0],
0094     .io_resource = &primary_pci_io_res,
0095 };
0096
0097 #ifdef CONFIG_64BIT
0098 int txx9_pci_mem_high __initdata = 1;
0099 #else
0100 int txx9_pci_mem_high __initdata;
0101 #endif
0102
0103 /*
0104  * allocate pci_controller and resources.
0105  * mem_base, io_base: physical address.  0 for auto assignment.
0106  * mem_size and io_size means max size on auto assignment.
0107  * pcic must be &txx9_primary_pcic or NULL.
0108  */
0109 struct pci_controller *__init
0110 txx9_alloc_pci_controller(struct pci_controller *pcic,
0111               unsigned long mem_base, unsigned long mem_size,
0112               unsigned long io_base, unsigned long io_size)
0113 {
0114     struct pcic {
0115         struct pci_controller c;
0116         struct resource r_mem[2];
0117         struct resource r_io;
0118     } *new = NULL;
0119     int min_size = 0x10000;
0120
0121     if (!pcic) {
0122         new = kzalloc(sizeof(*new), GFP_KERNEL);
0123         if (!new)
0124             return NULL;
0125         new->r_mem[0].name = "PCI mem";
0126         new->r_mem[1].name = "PCI mmio";
0127         new->r_io.name = "PCI io";
0128         new->c.mem_resource = new->r_mem;
0129         new->c.io_resource = &new->r_io;
0130         pcic = &new->c;
0131     } else
0132         BUG_ON(pcic != &txx9_primary_pcic);
0133     pcic->io_resource->flags = IORESOURCE_IO;
0134
0135     /*
0136      * for auto assignment, first search a (big) region for PCI
0137      * MEM, then search a region for PCI IO.
0138      */
0139     if (mem_base) {
0140         pcic->mem_resource[0].start = mem_base;
0141         pcic->mem_resource[0].end = mem_base + mem_size - 1;
0142         if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
0143             goto free_and_exit;
0144     } else {
0145         unsigned long min = 0, max = 0x20000000; /* low 512MB */
0146         if (!mem_size) {
0147             /* default size for auto assignment */
0148             if (txx9_pci_mem_high)
0149                 mem_size = 0x20000000;  /* mem:512M(max) */
0150             else
0151                 mem_size = 0x08000000;  /* mem:128M(max) */
0152         }
0153         if (txx9_pci_mem_high) {
0154             min = 0x20000000;
0155             max = 0xe0000000;
0156         }
0157         /* search free region for PCI MEM */
0158         for (; mem_size >= min_size; mem_size /= 2) {
0159             if (allocate_resource(&iomem_resource,
0160                           &pcic->mem_resource[0],
0161                           mem_size, min, max,
0162                           mem_size, NULL, NULL) == 0)
0163                 break;
0164         }
0165         if (mem_size < min_size)
0166             goto free_and_exit;
0167     }
0168
0169     pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
0170     if (io_base) {
0171         pcic->mem_resource[1].start = io_base;
0172         pcic->mem_resource[1].end = io_base + io_size - 1;
0173         if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
0174             goto release_and_exit;
0175     } else {
0176         if (!io_size)
0177             /* default size for auto assignment */
0178             io_size = 0x01000000;   /* io:16M(max) */
0179         /* search free region for PCI IO in low 512MB */
0180         for (; io_size >= min_size; io_size /= 2) {
0181             if (allocate_resource(&iomem_resource,
0182                           &pcic->mem_resource[1],
0183                           io_size, 0, 0x20000000,
0184                           io_size, NULL, NULL) == 0)
0185                 break;
0186         }
0187         if (io_size < min_size)
0188             goto release_and_exit;
0189         io_base = pcic->mem_resource[1].start;
0190     }
0191
0192     pcic->mem_resource[0].flags = IORESOURCE_MEM;
0193     if (pcic == &txx9_primary_pcic &&
0194         mips_io_port_base == (unsigned long)-1) {
0195         /* map ioport 0 to PCI I/O space address 0 */
0196         set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
0197         pcic->io_resource->start = 0;
0198         pcic->io_offset = 0;    /* busaddr == ioaddr */
0199         pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
0200     } else {
0201         /* physaddr to ioaddr */
0202         pcic->io_resource->start =
0203             io_base - (mips_io_port_base - IO_BASE);
0204         pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
0205         pcic->io_map_base = mips_io_port_base;
0206     }
0207     pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
0208
0209     pcic->mem_offset = 0;   /* busaddr == physaddr */
0210
0211     pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1],
0212         &pcic->mem_resource[0]);
0213
0214     /* register_pci_controller() will request MEM resource */
0215     release_resource(&pcic->mem_resource[0]);
0216     return pcic;
0217  release_and_exit:
0218     release_resource(&pcic->mem_resource[0]);
0219  free_and_exit:
0220     kfree(new);
0221     pr_err("PCI: Failed to allocate resources.\n");
0222     return NULL;
0223 }
0224
0225 static int __init
0226 txx9_arch_pci_init(void)
0227 {
0228     PCIBIOS_MIN_IO = 0x8000;    /* reserve legacy I/O space */
0229     return 0;
0230 }
0231 arch_initcall(txx9_arch_pci_init);
0232
0233 /* IRQ/IDSEL mapping */
0234 int txx9_pci_option =
0235 #ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
0236     TXX9_PCI_OPT_PICMG |
0237 #endif
0238     TXX9_PCI_OPT_CLK_AUTO;
0239
0240 enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
0241
0242 #ifdef CONFIG_TOSHIBA_FPCIB0
0243 static irqreturn_t i8259_interrupt(int irq, void *dev_id)
0244 {
0245     int isairq;
0246
0247     isairq = i8259_irq();
0248     if (unlikely(isairq <= I8259A_IRQ_BASE))
0249         return IRQ_NONE;
0250     generic_handle_irq(isairq);
0251     return IRQ_HANDLED;
0252 }
0253
0254 static int txx9_i8259_irq_setup(int irq)
0255 {
0256     int err;
0257
0258     init_i8259_irqs();
0259     err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
0260               "cascade(i8259)", (void *)(long)irq);
0261     if (!err)
0262         pr_info("PCI-ISA bridge PIC (irq %d)\n", irq);
0263     return err;
0264 }
0265
0266 static void __ref quirk_slc90e66_bridge(struct pci_dev *dev)
0267 {
0268     int irq;    /* PCI/ISA Bridge interrupt */
0269     u8 reg_64;
0270     u32 reg_b0;
0271     u8 reg_e1;
0272     irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
0273     if (!irq)
0274         return;
0275     txx9_i8259_irq_setup(irq);
0276     pci_read_config_byte(dev, 0x64, &reg_64);
0277     pci_read_config_dword(dev, 0xb0, &reg_b0);
0278     pci_read_config_byte(dev, 0xe1, &reg_e1);
0279     /* serial irq control */
0280     reg_64 = 0xd0;
0281     /* serial irq pin */
0282     reg_b0 |= 0x00010000;
0283     /* ide irq on isa14 */
0284     reg_e1 &= 0xf0;
0285     reg_e1 |= 0x0d;
0286     pci_write_config_byte(dev, 0x64, reg_64);
0287     pci_write_config_dword(dev, 0xb0, reg_b0);
0288     pci_write_config_byte(dev, 0xe1, reg_e1);
0289
0290     smsc_fdc37m81x_init(0x3f0);
0291     smsc_fdc37m81x_config_beg();
0292     smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
0293                   SMSC_FDC37M81X_KBD);
0294     smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
0295     smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
0296     smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
0297                   1);
0298     smsc_fdc37m81x_config_end();
0299 }
0300
0301 static void quirk_slc90e66_ide(struct pci_dev *dev)
0302 {
0303     unsigned char dat;
0304     int regs[2] = {0x41, 0x43};
0305     int i;
0306
0307     /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
0308     pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
0309     pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
0310     pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat);
0311     /* enable SMSC SLC90E66 IDE */
0312     for (i = 0; i < ARRAY_SIZE(regs); i++) {
0313         pci_read_config_byte(dev, regs[i], &dat);
0314         pci_write_config_byte(dev, regs[i], dat | 0x80);
0315         pci_read_config_byte(dev, regs[i], &dat);
0316         pr_cont(" IDETIM%d %02x", i, dat);
0317     }
0318     pci_read_config_byte(dev, 0x5c, &dat);
0319     /*
0320      * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
0321      *
0322      * This line of code is intended to provide the user with a work
0323      * around solution to the anomalies cited in SMSC's anomaly sheet
0324      * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
0325      *
0326      * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
0327      */
0328     dat |= 0x01;
0329     pci_write_config_byte(dev, 0x5c, dat);
0330     pci_read_config_byte(dev, 0x5c, &dat);
0331     pr_cont(" REG5C %02x\n", dat);
0332 }
0333 #endif /* CONFIG_TOSHIBA_FPCIB0 */
0334
0335 static void tc35815_fixup(struct pci_dev *dev)
0336 {
0337     /* This device may have PM registers but not they are not supported. */
0338     if (dev->pm_cap) {
0339         dev_info(&dev->dev, "PM disabled\n");
0340         dev->pm_cap = 0;
0341     }
0342 }
0343
0344 static void final_fixup(struct pci_dev *dev)
0345 {
0346     unsigned char bist;
0347
0348     /* Do build-in self test */
0349     if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
0350         (bist & PCI_BIST_CAPABLE)) {
0351         unsigned long timeout;
0352         pci_set_power_state(dev, PCI_D0);
0353         pr_info("PCI: %s BIST...", pci_name(dev));
0354         pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
0355         timeout = jiffies + HZ * 2; /* timeout after 2 sec */
0356         do {
0357             pci_read_config_byte(dev, PCI_BIST, &bist);
0358             if (time_after(jiffies, timeout))
0359                 break;
0360         } while (bist & PCI_BIST_START);
0361         if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
0362             pr_cont("failed. (0x%x)\n", bist);
0363         else
0364             pr_cont("OK.\n");
0365     }
0366 }
0367
0368 #ifdef CONFIG_TOSHIBA_FPCIB0
0369 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
0370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
0371     quirk_slc90e66_bridge);
0372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
0373     quirk_slc90e66_ide);
0374 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
0375     quirk_slc90e66_ide);
0376 #endif
0377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
0378             PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
0379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
0380             PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
0381 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
0382 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
0383
0384 int pcibios_plat_dev_init(struct pci_dev *dev)
0385 {
0386     return 0;
0387 }
0388
0389 static int (*txx9_pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
0390 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0391 {
0392     return txx9_pci_map_irq(dev, slot, pin);
0393 }
0394
0395 char * (*txx9_board_pcibios_setup)(char *str) __initdata;
0396
0397 char *__init txx9_pcibios_setup(char *str)
0398 {
0399     if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
0400         return NULL;
0401     if (!strcmp(str, "picmg")) {
0402         /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
0403            (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
0404         txx9_pci_option |= TXX9_PCI_OPT_PICMG;
0405         return NULL;
0406     } else if (!strcmp(str, "nopicmg")) {
0407         /* non-PICMG compliant backplane (TOSHIBA
0408            RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
0409         txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
0410         return NULL;
0411     } else if (!strncmp(str, "clk=", 4)) {
0412         char *val = str + 4;
0413         txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
0414         if (strcmp(val, "33") == 0)
0415             txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
0416         else if (strcmp(val, "66") == 0)
0417             txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
0418         else /* "auto" */
0419             txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
0420         return NULL;
0421     } else if (!strncmp(str, "err=", 4)) {
0422         if (!strcmp(str + 4, "panic"))
0423             txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
0424         else if (!strcmp(str + 4, "ignore"))
0425             txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
0426         return NULL;
0427     }
0428
0429     txx9_pci_map_irq = txx9_board_vec->pci_map_irq;
0430
0431     return str;
0432 }