mips/sni/time.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/types.h>
0003 #include <linux/i8253.h>
0004 #include <linux/interrupt.h>
0005 #include <linux/irq.h>
0006 #include <linux/smp.h>
0007 #include <linux/time.h>
0008 #include <linux/clockchips.h>
0009
0010 #include <asm/sni.h>
0011 #include <asm/time.h>
0012
0013 #define SNI_CLOCK_TICK_RATE 3686400
0014 #define SNI_COUNTER2_DIV    64
0015 #define SNI_COUNTER0_DIV    ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
0016
0017 static int a20r_set_periodic(struct clock_event_device *evt)
0018 {
0019     *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34;
0020     wmb();
0021     *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV & 0xff;
0022     wmb();
0023     *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV >> 8;
0024     wmb();
0025
0026     *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4;
0027     wmb();
0028     *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV & 0xff;
0029     wmb();
0030     *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV >> 8;
0031     wmb();
0032     return 0;
0033 }
0034
0035 static struct clock_event_device a20r_clockevent_device = {
0036     .name           = "a20r-timer",
0037     .features       = CLOCK_EVT_FEAT_PERIODIC,
0038
0039     /* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
0040
0041     .rating         = 300,
0042     .irq            = SNI_A20R_IRQ_TIMER,
0043     .set_state_periodic = a20r_set_periodic,
0044 };
0045
0046 static irqreturn_t a20r_interrupt(int irq, void *dev_id)
0047 {
0048     struct clock_event_device *cd = dev_id;
0049
0050     *(volatile u8 *)A20R_PT_TIM0_ACK = 0;
0051     wmb();
0052
0053     cd->event_handler(cd);
0054
0055     return IRQ_HANDLED;
0056 }
0057
0058 /*
0059  * a20r platform uses 2 counters to divide the input frequency.
0060  * Counter 2 output is connected to Counter 0 & 1 input.
0061  */
0062 static void __init sni_a20r_timer_setup(void)
0063 {
0064     struct clock_event_device *cd = &a20r_clockevent_device;
0065     unsigned int cpu = smp_processor_id();
0066
0067     cd->cpumask     = cpumask_of(cpu);
0068     clockevents_register_device(cd);
0069     if (request_irq(SNI_A20R_IRQ_TIMER, a20r_interrupt,
0070             IRQF_PERCPU | IRQF_TIMER, "a20r-timer", cd))
0071         pr_err("Failed to register a20r-timer interrupt\n");
0072 }
0073
0074 #define SNI_8254_TICK_RATE    1193182UL
0075
0076 #define SNI_8254_TCSAMP_COUNTER   ((SNI_8254_TICK_RATE / HZ) + 255)
0077
0078 static __init unsigned long dosample(void)
0079 {
0080     u32 ct0, ct1;
0081     volatile u8 msb;
0082
0083     /* Start the counter. */
0084     outb_p(0x34, 0x43);
0085     outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
0086     outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
0087
0088     /* Get initial counter invariant */
0089     ct0 = read_c0_count();
0090
0091     /* Latch and spin until top byte of counter0 is zero */
0092     do {
0093         outb(0x00, 0x43);
0094         (void) inb(0x40);
0095         msb = inb(0x40);
0096         ct1 = read_c0_count();
0097     } while (msb);
0098
0099     /* Stop the counter. */
0100     outb(0x38, 0x43);
0101     /*
0102      * Return the difference, this is how far the r4k counter increments
0103      * for every 1/HZ seconds. We round off the nearest 1 MHz of master
0104      * clock (= 1000000 / HZ / 2).
0105      */
0106     /*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
0107     return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
0108 }
0109
0110 /*
0111  * Here we need to calibrate the cycle counter to at least be close.
0112  */
0113 void __init plat_time_init(void)
0114 {
0115     unsigned long r4k_ticks[3];
0116     unsigned long r4k_tick;
0117
0118     /*
0119      * Figure out the r4k offset, the algorithm is very simple and works in
0120      * _all_ cases as long as the 8254 counter register itself works ok (as
0121      * an interrupt driving timer it does not because of bug, this is why
0122      * we are using the onchip r4k counter/compare register to serve this
0123      * purpose, but for r4k_offset calculation it will work ok for us).
0124      * There are other very complicated ways of performing this calculation
0125      * but this one works just fine so I am not going to futz around. ;-)
0126      */
0127     printk(KERN_INFO "Calibrating system timer... ");
0128     dosample(); /* Prime cache. */
0129     dosample(); /* Prime cache. */
0130     /* Zero is NOT an option. */
0131     do {
0132         r4k_ticks[0] = dosample();
0133     } while (!r4k_ticks[0]);
0134     do {
0135         r4k_ticks[1] = dosample();
0136     } while (!r4k_ticks[1]);
0137
0138     if (r4k_ticks[0] != r4k_ticks[1]) {
0139         printk("warning: timer counts differ, retrying... ");
0140         r4k_ticks[2] = dosample();
0141         if (r4k_ticks[2] == r4k_ticks[0]
0142             || r4k_ticks[2] == r4k_ticks[1])
0143             r4k_tick = r4k_ticks[2];
0144         else {
0145             printk("disagreement, using average... ");
0146             r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
0147                    + r4k_ticks[2]) / 3;
0148         }
0149     } else
0150         r4k_tick = r4k_ticks[0];
0151
0152     printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
0153         (int) (r4k_tick / (500000 / HZ)),
0154         (int) (r4k_tick % (500000 / HZ)));
0155
0156     mips_hpt_frequency = r4k_tick * HZ;
0157
0158     switch (sni_brd_type) {
0159     case SNI_BRD_10:
0160     case SNI_BRD_10NEW:
0161     case SNI_BRD_TOWER_OASIC:
0162     case SNI_BRD_MINITOWER:
0163         sni_a20r_timer_setup();
0164         break;
0165     }
0166     setup_pit_timer();
0167 }