mips/sni/a20r.c

0001 /*
0002  * A20R specific code
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
0009  */
0010
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/irq.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/serial_8250.h>
0016
0017 #include <asm/sni.h>
0018 #include <asm/time.h>
0019
0020 #define PORT(_base,_irq)                \
0021     {                       \
0022         .iobase     = _base,        \
0023         .irq        = _irq,         \
0024         .uartclk    = 1843200,      \
0025         .iotype     = UPIO_PORT,        \
0026         .flags      = UPF_BOOT_AUTOCONF,    \
0027     }
0028
0029 static struct plat_serial8250_port a20r_data[] = {
0030     PORT(0x3f8, 4),
0031     PORT(0x2f8, 3),
0032     { },
0033 };
0034
0035 static struct platform_device a20r_serial8250_device = {
0036     .name           = "serial8250",
0037     .id         = PLAT8250_DEV_PLATFORM,
0038     .dev            = {
0039         .platform_data  = a20r_data,
0040     },
0041 };
0042
0043 static struct resource a20r_ds1216_rsrc[] = {
0044     {
0045         .start = 0x1c081ffc,
0046         .end   = 0x1c081fff,
0047         .flags = IORESOURCE_MEM
0048     }
0049 };
0050
0051 static struct platform_device a20r_ds1216_device = {
0052     .name       = "rtc-ds1216",
0053     .num_resources  = ARRAY_SIZE(a20r_ds1216_rsrc),
0054     .resource   = a20r_ds1216_rsrc
0055 };
0056
0057 static struct resource snirm_82596_rsrc[] = {
0058     {
0059         .start = 0x18000000,
0060         .end   = 0x18000004,
0061         .flags = IORESOURCE_MEM
0062     },
0063     {
0064         .start = 0x18010000,
0065         .end   = 0x18010004,
0066         .flags = IORESOURCE_MEM
0067     },
0068     {
0069         .start = 0x1ff00000,
0070         .end   = 0x1ff00020,
0071         .flags = IORESOURCE_MEM
0072     },
0073     {
0074         .start = 22,
0075         .end   = 22,
0076         .flags = IORESOURCE_IRQ
0077     },
0078     {
0079         .flags = 0x01            /* 16bit mpu port access */
0080     }
0081 };
0082
0083 static struct platform_device snirm_82596_pdev = {
0084     .name       = "snirm_82596",
0085     .num_resources  = ARRAY_SIZE(snirm_82596_rsrc),
0086     .resource   = snirm_82596_rsrc
0087 };
0088
0089 static struct resource snirm_53c710_rsrc[] = {
0090     {
0091         .start = 0x19000000,
0092         .end   = 0x190fffff,
0093         .flags = IORESOURCE_MEM
0094     },
0095     {
0096         .start = 19,
0097         .end   = 19,
0098         .flags = IORESOURCE_IRQ
0099     }
0100 };
0101
0102 static struct platform_device snirm_53c710_pdev = {
0103     .name       = "snirm_53c710",
0104     .num_resources  = ARRAY_SIZE(snirm_53c710_rsrc),
0105     .resource   = snirm_53c710_rsrc
0106 };
0107
0108 static struct resource sc26xx_rsrc[] = {
0109     {
0110         .start = 0x1c070000,
0111         .end   = 0x1c0700ff,
0112         .flags = IORESOURCE_MEM
0113     },
0114     {
0115         .start = 20,
0116         .end   = 20,
0117         .flags = IORESOURCE_IRQ
0118     }
0119 };
0120
0121 #include <linux/platform_data/serial-sccnxp.h>
0122
0123 static struct sccnxp_pdata sccnxp_data = {
0124     .reg_shift  = 2,
0125     .mctrl_cfg[0]   = MCTRL_SIG(DTR_OP, LINE_OP7) |
0126               MCTRL_SIG(RTS_OP, LINE_OP3) |
0127               MCTRL_SIG(DSR_IP, LINE_IP5) |
0128               MCTRL_SIG(DCD_IP, LINE_IP6),
0129     .mctrl_cfg[1]   = MCTRL_SIG(DTR_OP, LINE_OP2) |
0130               MCTRL_SIG(RTS_OP, LINE_OP1) |
0131               MCTRL_SIG(DSR_IP, LINE_IP0) |
0132               MCTRL_SIG(CTS_IP, LINE_IP1) |
0133               MCTRL_SIG(DCD_IP, LINE_IP2) |
0134               MCTRL_SIG(RNG_IP, LINE_IP3),
0135 };
0136
0137 static struct platform_device sc26xx_pdev = {
0138     .name       = "sc2681",
0139     .resource   = sc26xx_rsrc,
0140     .num_resources  = ARRAY_SIZE(sc26xx_rsrc),
0141     .dev    = {
0142         .platform_data  = &sccnxp_data,
0143     },
0144 };
0145
0146 /*
0147  * Trigger chipset to update CPU's CAUSE IP field
0148  */
0149 static u32 a20r_update_cause_ip(void)
0150 {
0151     u32 status = read_c0_status();
0152
0153     write_c0_status(status | 0x00010000);
0154     asm volatile(
0155     "   .set    push            \n"
0156     "   .set    noat            \n"
0157     "   .set    noreorder       \n"
0158     "   lw  $1, 0(%0)       \n"
0159     "   sb  $0, 0(%1)       \n"
0160     "   sync                \n"
0161     "   lb  %1, 0(%1)       \n"
0162     "   b   1f          \n"
0163     "   ori %1, $1, 2       \n"
0164     "   .align  8           \n"
0165     "1:                 \n"
0166     "   nop             \n"
0167     "   sw  %1, 0(%0)       \n"
0168     "   sync                \n"
0169     "   li  %1, 0x20        \n"
0170     "2:                 \n"
0171     "   nop             \n"
0172     "   bnez    %1,2b           \n"
0173     "   addiu   %1, -1          \n"
0174     "   sw  $1, 0(%0)       \n"
0175     "   sync                \n"
0176         ".set   pop         \n"
0177     :
0178     : "Jr" (PCIMT_UCONF), "Jr" (0xbc000000));
0179     write_c0_status(status);
0180
0181     return status;
0182 }
0183
0184 static inline void unmask_a20r_irq(struct irq_data *d)
0185 {
0186     set_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE));
0187     irq_enable_hazard();
0188 }
0189
0190 static inline void mask_a20r_irq(struct irq_data *d)
0191 {
0192     clear_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE));
0193     irq_disable_hazard();
0194 }
0195
0196 static struct irq_chip a20r_irq_type = {
0197     .name       = "A20R",
0198     .irq_mask   = mask_a20r_irq,
0199     .irq_unmask = unmask_a20r_irq,
0200 };
0201
0202 /*
0203  * hwint 0 receive all interrupts
0204  */
0205 static void a20r_hwint(void)
0206 {
0207     u32 cause, status;
0208     int irq;
0209
0210     clear_c0_status(IE_IRQ0);
0211     status = a20r_update_cause_ip();
0212     cause = read_c0_cause();
0213
0214     irq = ffs(((cause & status) >> 8) & 0xf8);
0215     if (likely(irq > 0))
0216         do_IRQ(SNI_A20R_IRQ_BASE + irq - 1);
0217
0218     a20r_update_cause_ip();
0219     set_c0_status(IE_IRQ0);
0220 }
0221
0222 void __init sni_a20r_irq_init(void)
0223 {
0224     int i;
0225
0226     for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
0227         irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
0228     sni_hwint = a20r_hwint;
0229     change_c0_status(ST0_IM, IE_IRQ0);
0230     if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler,
0231             IRQF_SHARED, "ISA", sni_isa_irq_handler))
0232         pr_err("Failed to register ISA interrupt\n");
0233 }
0234
0235 void sni_a20r_init(void)
0236 {
0237     /* FIXME, remove if not needed */
0238 }
0239
0240 static int __init snirm_a20r_setup_devinit(void)
0241 {
0242     switch (sni_brd_type) {
0243     case SNI_BRD_TOWER_OASIC:
0244     case SNI_BRD_MINITOWER:
0245         platform_device_register(&snirm_82596_pdev);
0246         platform_device_register(&snirm_53c710_pdev);
0247         platform_device_register(&sc26xx_pdev);
0248         platform_device_register(&a20r_serial8250_device);
0249         platform_device_register(&a20r_ds1216_device);
0250         sni_eisa_root_init();
0251         break;
0252     }
0253     return 0;
0254 }
0255
0256 device_initcall(snirm_a20r_setup_devinit);