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0011 #include <linux/spinlock.h>
0012 #include <linux/mm.h>
0013 #include <linux/memblock.h>
0014 #include <linux/init.h>
0015 #include <linux/kernel.h>
0016 #include <linux/screen_info.h>
0017 #include <linux/initrd.h>
0018
0019 #include <asm/irq.h>
0020 #include <asm/io.h>
0021 #include <asm/bootinfo.h>
0022 #include <asm/mipsregs.h>
0023 #include <asm/reboot.h>
0024 #include <asm/time.h>
0025 #include <asm/traps.h>
0026 #include <asm/sibyte/sb1250.h>
0027 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
0028 #include <asm/sibyte/bcm1480_regs.h>
0029 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
0030 #include <asm/sibyte/sb1250_regs.h>
0031 #else
0032 #error invalid SiByte board configuration
0033 #endif
0034 #include <asm/sibyte/sb1250_genbus.h>
0035 #include <asm/sibyte/board.h>
0036
0037 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
0038 extern void bcm1480_setup(void);
0039 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
0040 extern void sb1250_setup(void);
0041 #else
0042 #error invalid SiByte board configuration
0043 #endif
0044
0045 extern int xicor_probe(void);
0046 extern int xicor_set_time(time64_t);
0047 extern time64_t xicor_get_time(void);
0048
0049 extern int m41t81_probe(void);
0050 extern int m41t81_set_time(time64_t);
0051 extern time64_t m41t81_get_time(void);
0052
0053 const char *get_system_type(void)
0054 {
0055 return "SiByte " SIBYTE_BOARD_NAME;
0056 }
0057
0058 int swarm_be_handler(struct pt_regs *regs, int is_fixup)
0059 {
0060 if (!is_fixup && (regs->cp0_cause & 4)) {
0061
0062 printk("DBE physical address: %010Lx\n",
0063 __read_64bit_c0_register($26, 1));
0064 }
0065 return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
0066 }
0067
0068 enum swarm_rtc_type {
0069 RTC_NONE,
0070 RTC_XICOR,
0071 RTC_M41T81,
0072 };
0073
0074 enum swarm_rtc_type swarm_rtc_type;
0075
0076 void read_persistent_clock64(struct timespec64 *ts)
0077 {
0078 time64_t sec;
0079
0080 switch (swarm_rtc_type) {
0081 case RTC_XICOR:
0082 sec = xicor_get_time();
0083 break;
0084
0085 case RTC_M41T81:
0086 sec = m41t81_get_time();
0087 break;
0088
0089 case RTC_NONE:
0090 default:
0091 sec = mktime64(2000, 1, 1, 0, 0, 0);
0092 break;
0093 }
0094 ts->tv_sec = sec;
0095 ts->tv_nsec = 0;
0096 }
0097
0098 int update_persistent_clock64(struct timespec64 now)
0099 {
0100 time64_t sec = now.tv_sec;
0101
0102 switch (swarm_rtc_type) {
0103 case RTC_XICOR:
0104 return xicor_set_time(sec);
0105
0106 case RTC_M41T81:
0107 return m41t81_set_time(sec);
0108
0109 case RTC_NONE:
0110 default:
0111 return -1;
0112 }
0113 }
0114
0115 void __init plat_mem_setup(void)
0116 {
0117 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
0118 bcm1480_setup();
0119 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
0120 sb1250_setup();
0121 #else
0122 #error invalid SiByte board configuration
0123 #endif
0124
0125 mips_set_be_handler(swarm_be_handler);
0126
0127 if (xicor_probe())
0128 swarm_rtc_type = RTC_XICOR;
0129 if (m41t81_probe())
0130 swarm_rtc_type = RTC_M41T81;
0131
0132 #ifdef CONFIG_VT
0133 screen_info = (struct screen_info) {
0134 .orig_video_page = 52,
0135 .orig_video_mode = 3,
0136 .orig_video_cols = 80,
0137 .flags = 12,
0138 .orig_video_ega_bx = 3,
0139 .orig_video_lines = 25,
0140 .orig_video_isVGA = 0x22,
0141 .orig_video_points = 16,
0142 };
0143
0144 #endif
0145 }
0146
0147 #ifdef LEDS_PHYS
0148
0149 #ifdef CONFIG_SIBYTE_CARMEL
0150
0151 #undef LEDS_PHYS
0152 #define LEDS_PHYS MLEDS_PHYS
0153 #endif
0154
0155 void setleds(char *str)
0156 {
0157 void *reg;
0158 int i;
0159
0160 for (i = 0; i < 4; i++) {
0161 reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3);
0162
0163 if (!str[i])
0164 writeb(' ', reg);
0165 else
0166 writeb(str[i], reg);
0167 }
0168 }
0169
0170 #endif