sibyte/swarm/rtc_m41t81.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2000, 2001 Broadcom Corporation
0004  *
0005  * Copyright (C) 2002 MontaVista Software Inc.
0006  * Author: jsun@mvista.com or jsun@junsun.net
0007  */
0008 #include <linux/bcd.h>
0009 #include <linux/types.h>
0010 #include <linux/time.h>
0011
0012 #include <asm/time.h>
0013 #include <asm/addrspace.h>
0014 #include <asm/io.h>
0015
0016 #include <asm/sibyte/sb1250.h>
0017 #include <asm/sibyte/sb1250_regs.h>
0018 #include <asm/sibyte/sb1250_smbus.h>
0019
0020
0021 /* M41T81 definitions */
0022
0023 /*
0024  * Register bits
0025  */
0026
0027 #define M41T81REG_SC_ST     0x80        /* stop bit */
0028 #define M41T81REG_HR_CB     0x40        /* century bit */
0029 #define M41T81REG_HR_CEB    0x80        /* century enable bit */
0030 #define M41T81REG_CTL_S     0x20        /* sign bit */
0031 #define M41T81REG_CTL_FT    0x40        /* frequency test bit */
0032 #define M41T81REG_CTL_OUT   0x80        /* output level */
0033 #define M41T81REG_WD_RB0    0x01        /* watchdog resolution bit 0 */
0034 #define M41T81REG_WD_RB1    0x02        /* watchdog resolution bit 1 */
0035 #define M41T81REG_WD_BMB0   0x04        /* watchdog multiplier bit 0 */
0036 #define M41T81REG_WD_BMB1   0x08        /* watchdog multiplier bit 1 */
0037 #define M41T81REG_WD_BMB2   0x10        /* watchdog multiplier bit 2 */
0038 #define M41T81REG_WD_BMB3   0x20        /* watchdog multiplier bit 3 */
0039 #define M41T81REG_WD_BMB4   0x40        /* watchdog multiplier bit 4 */
0040 #define M41T81REG_AMO_ABE   0x20        /* alarm in "battery back-up mode" enable bit */
0041 #define M41T81REG_AMO_SQWE  0x40        /* square wave enable */
0042 #define M41T81REG_AMO_AFE   0x80        /* alarm flag enable flag */
0043 #define M41T81REG_ADT_RPT5  0x40        /* alarm repeat mode bit 5 */
0044 #define M41T81REG_ADT_RPT4  0x80        /* alarm repeat mode bit 4 */
0045 #define M41T81REG_AHR_RPT3  0x80        /* alarm repeat mode bit 3 */
0046 #define M41T81REG_AHR_HT    0x40        /* halt update bit */
0047 #define M41T81REG_AMN_RPT2  0x80        /* alarm repeat mode bit 2 */
0048 #define M41T81REG_ASC_RPT1  0x80        /* alarm repeat mode bit 1 */
0049 #define M41T81REG_FLG_AF    0x40        /* alarm flag (read only) */
0050 #define M41T81REG_FLG_WDF   0x80        /* watchdog flag (read only) */
0051 #define M41T81REG_SQW_RS0   0x10        /* sqw frequency bit 0 */
0052 #define M41T81REG_SQW_RS1   0x20        /* sqw frequency bit 1 */
0053 #define M41T81REG_SQW_RS2   0x40        /* sqw frequency bit 2 */
0054 #define M41T81REG_SQW_RS3   0x80        /* sqw frequency bit 3 */
0055
0056
0057 /*
0058  * Register numbers
0059  */
0060
0061 #define M41T81REG_TSC   0x00        /* tenths/hundredths of second */
0062 #define M41T81REG_SC    0x01        /* seconds */
0063 #define M41T81REG_MN    0x02        /* minute */
0064 #define M41T81REG_HR    0x03        /* hour/century */
0065 #define M41T81REG_DY    0x04        /* day of week */
0066 #define M41T81REG_DT    0x05        /* date of month */
0067 #define M41T81REG_MO    0x06        /* month */
0068 #define M41T81REG_YR    0x07        /* year */
0069 #define M41T81REG_CTL   0x08        /* control */
0070 #define M41T81REG_WD    0x09        /* watchdog */
0071 #define M41T81REG_AMO   0x0A        /* alarm: month */
0072 #define M41T81REG_ADT   0x0B        /* alarm: date */
0073 #define M41T81REG_AHR   0x0C        /* alarm: hour */
0074 #define M41T81REG_AMN   0x0D        /* alarm: minute */
0075 #define M41T81REG_ASC   0x0E        /* alarm: second */
0076 #define M41T81REG_FLG   0x0F        /* flags */
0077 #define M41T81REG_SQW   0x13        /* square wave register */
0078
0079 #define M41T81_CCR_ADDRESS  0x68
0080
0081 #define SMB_CSR(reg)    IOADDR(A_SMB_REGISTER(1, reg))
0082
0083 static int m41t81_read(uint8_t addr)
0084 {
0085     while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
0086         ;
0087
0088     __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
0089     __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE,
0090              SMB_CSR(R_SMB_START));
0091
0092     while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
0093         ;
0094
0095     __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
0096              SMB_CSR(R_SMB_START));
0097
0098     while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
0099         ;
0100
0101     if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
0102         /* Clear error bit by writing a 1 */
0103         __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
0104         return -1;
0105     }
0106
0107     return __raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff;
0108 }
0109
0110 static int m41t81_write(uint8_t addr, int b)
0111 {
0112     while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
0113         ;
0114
0115     __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
0116     __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA));
0117     __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
0118              SMB_CSR(R_SMB_START));
0119
0120     while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
0121         ;
0122
0123     if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
0124         /* Clear error bit by writing a 1 */
0125         __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
0126         return -1;
0127     }
0128
0129     /* read the same byte again to make sure it is written */
0130     __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
0131              SMB_CSR(R_SMB_START));
0132
0133     while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
0134         ;
0135
0136     return 0;
0137 }
0138
0139 int m41t81_set_time(time64_t t)
0140 {
0141     struct rtc_time tm;
0142     unsigned long flags;
0143
0144     /* Note we don't care about the century */
0145     rtc_time64_to_tm(t, &tm);
0146
0147     /*
0148      * Note the write order matters as it ensures the correctness.
0149      * When we write sec, 10th sec is clear.  It is reasonable to
0150      * believe we should finish writing min within a second.
0151      */
0152
0153     spin_lock_irqsave(&rtc_lock, flags);
0154     tm.tm_sec = bin2bcd(tm.tm_sec);
0155     m41t81_write(M41T81REG_SC, tm.tm_sec);
0156
0157     tm.tm_min = bin2bcd(tm.tm_min);
0158     m41t81_write(M41T81REG_MN, tm.tm_min);
0159
0160     tm.tm_hour = bin2bcd(tm.tm_hour);
0161     tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0);
0162     m41t81_write(M41T81REG_HR, tm.tm_hour);
0163
0164     /* tm_wday starts from 0 to 6 */
0165     if (tm.tm_wday == 0) tm.tm_wday = 7;
0166     tm.tm_wday = bin2bcd(tm.tm_wday);
0167     m41t81_write(M41T81REG_DY, tm.tm_wday);
0168
0169     tm.tm_mday = bin2bcd(tm.tm_mday);
0170     m41t81_write(M41T81REG_DT, tm.tm_mday);
0171
0172     /* tm_mon starts from 0, *ick* */
0173     tm.tm_mon ++;
0174     tm.tm_mon = bin2bcd(tm.tm_mon);
0175     m41t81_write(M41T81REG_MO, tm.tm_mon);
0176
0177     /* we don't do century, everything is beyond 2000 */
0178     tm.tm_year %= 100;
0179     tm.tm_year = bin2bcd(tm.tm_year);
0180     m41t81_write(M41T81REG_YR, tm.tm_year);
0181     spin_unlock_irqrestore(&rtc_lock, flags);
0182
0183     return 0;
0184 }
0185
0186 time64_t m41t81_get_time(void)
0187 {
0188     unsigned int year, mon, day, hour, min, sec;
0189     unsigned long flags;
0190
0191     /*
0192      * min is valid if two reads of sec are the same.
0193      */
0194     for (;;) {
0195         spin_lock_irqsave(&rtc_lock, flags);
0196         sec = m41t81_read(M41T81REG_SC);
0197         min = m41t81_read(M41T81REG_MN);
0198         if (sec == m41t81_read(M41T81REG_SC)) break;
0199         spin_unlock_irqrestore(&rtc_lock, flags);
0200     }
0201     hour = m41t81_read(M41T81REG_HR) & 0x3f;
0202     day = m41t81_read(M41T81REG_DT);
0203     mon = m41t81_read(M41T81REG_MO);
0204     year = m41t81_read(M41T81REG_YR);
0205     spin_unlock_irqrestore(&rtc_lock, flags);
0206
0207     sec = bcd2bin(sec);
0208     min = bcd2bin(min);
0209     hour = bcd2bin(hour);
0210     day = bcd2bin(day);
0211     mon = bcd2bin(mon);
0212     year = bcd2bin(year);
0213
0214     year += 2000;
0215
0216     return mktime64(year, mon, day, hour, min, sec);
0217 }
0218
0219 int m41t81_probe(void)
0220 {
0221     unsigned int tmp;
0222
0223     /* enable chip if it is not enabled yet */
0224     tmp = m41t81_read(M41T81REG_SC);
0225     m41t81_write(M41T81REG_SC, tmp & 0x7f);
0226
0227     return m41t81_read(M41T81REG_SC) != -1;
0228 }