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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *
0004  * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
0005  * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
0006  * Copyright (C) 2007 MIPS Technologies, Inc.
0007  *    written by Ralf Baechle <ralf@linux-mips.org>
0008  */
0009 
0010 #undef DEBUG
0011 
0012 #include <linux/device.h>
0013 #include <linux/module.h>
0014 #include <linux/kernel.h>
0015 #include <linux/types.h>
0016 #include <linux/init.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/sched.h>
0019 #include <linux/vmalloc.h>
0020 #include <linux/fs.h>
0021 #include <linux/errno.h>
0022 #include <linux/wait.h>
0023 #include <asm/io.h>
0024 #include <asm/sibyte/sb1250.h>
0025 
0026 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
0027 #include <asm/sibyte/bcm1480_regs.h>
0028 #include <asm/sibyte/bcm1480_scd.h>
0029 #include <asm/sibyte/bcm1480_int.h>
0030 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
0031 #include <asm/sibyte/sb1250_regs.h>
0032 #include <asm/sibyte/sb1250_scd.h>
0033 #include <asm/sibyte/sb1250_int.h>
0034 #else
0035 #error invalid SiByte UART configuration
0036 #endif
0037 
0038 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
0039 #undef K_INT_TRACE_FREEZE
0040 #define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
0041 #undef K_INT_PERF_CNT
0042 #define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
0043 #endif
0044 
0045 #include <linux/uaccess.h>
0046 
0047 #define SBPROF_TB_MAJOR 240
0048 
0049 typedef u64 tb_sample_t[6*256];
0050 
0051 enum open_status {
0052     SB_CLOSED,
0053     SB_OPENING,
0054     SB_OPEN
0055 };
0056 
0057 struct sbprof_tb {
0058     wait_queue_head_t   tb_sync;
0059     wait_queue_head_t   tb_read;
0060     struct mutex        lock;
0061     enum open_status    open;
0062     tb_sample_t     *sbprof_tbbuf;
0063     int         next_tb_sample;
0064 
0065     volatile int        tb_enable;
0066     volatile int        tb_armed;
0067 
0068 };
0069 
0070 static struct sbprof_tb sbp;
0071 
0072 #define MAX_SAMPLE_BYTES (24*1024*1024)
0073 #define MAX_TBSAMPLE_BYTES (12*1024*1024)
0074 
0075 #define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
0076 #define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
0077 #define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
0078 
0079 /* ioctls */
0080 #define SBPROF_ZBSTART      _IOW('s', 0, int)
0081 #define SBPROF_ZBSTOP       _IOW('s', 1, int)
0082 #define SBPROF_ZBWAITFULL   _IOW('s', 2, int)
0083 
0084 /*
0085  * Routines for using 40-bit SCD cycle counter
0086  *
0087  * Client responsible for either handling interrupts or making sure
0088  * the cycles counter never saturates, e.g., by doing
0089  * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
0090  */
0091 
0092 /*
0093  * Configures SCD counter 0 to count ZCLKs starting from val;
0094  * Configures SCD counters1,2,3 to count nothing.
0095  * Must not be called while gathering ZBbus profiles.
0096  */
0097 
0098 #define zclk_timer_init(val) \
0099   __asm__ __volatile__ (".set push;" \
0100             ".set mips64;" \
0101             "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
0102             "sd   %0, 0x10($8);"   /* write val to counter0 */ \
0103             "sd   %1, 0($8);"      /* config counter0 for zclks*/ \
0104             ".set pop" \
0105             : /* no outputs */ \
0106                              /* enable, counter0 */ \
0107             : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
0108             : /* modifies */ "$8" )
0109 
0110 
0111 /* Reads SCD counter 0 and puts result in value
0112    unsigned long long val; */
0113 #define zclk_get(val) \
0114   __asm__ __volatile__ (".set push;" \
0115             ".set mips64;" \
0116             "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
0117             "ld   %0, 0x10($8);"   /* write val to counter0 */ \
0118             ".set pop" \
0119             : /* outputs */ "=r"(val) \
0120             : /* inputs */ \
0121             : /* modifies */ "$8" )
0122 
0123 #define DEVNAME "sb_tbprof"
0124 
0125 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
0126 
0127 /*
0128  * Support for ZBbus sampling using the trace buffer
0129  *
0130  * We use the SCD performance counter interrupt, caused by a Zclk counter
0131  * overflow, to trigger the start of tracing.
0132  *
0133  * We set the trace buffer to sample everything and freeze on
0134  * overflow.
0135  *
0136  * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
0137  *
0138  */
0139 
0140 static u64 tb_period;
0141 
0142 static void arm_tb(void)
0143 {
0144     u64 scdperfcnt;
0145     u64 next = (1ULL << 40) - tb_period;
0146     u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
0147 
0148     /*
0149      * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
0150      * trigger start of trace.  XXX vary sampling period
0151      */
0152     __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
0153     scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
0154 
0155     /*
0156      * Unfortunately, in Pass 2 we must clear all counters to knock down
0157      * a previous interrupt request.  This means that bus profiling
0158      * requires ALL of the SCD perf counters.
0159      */
0160 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
0161     __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
0162                         /* keep counters 0,2,3,4,5,6,7 as is */
0163              V_SPC_CFG_SRC1(1),     /* counter 1 counts cycles */
0164              IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0));
0165     __raw_writeq(
0166              M_SPC_CFG_ENABLE |     /* enable counting */
0167              M_SPC_CFG_CLEAR |      /* clear all counters */
0168              V_SPC_CFG_SRC1(1),     /* counter 1 counts cycles */
0169              IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1));
0170 #else
0171     __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
0172                         /* keep counters 0,2,3 as is */
0173              M_SPC_CFG_ENABLE |     /* enable counting */
0174              M_SPC_CFG_CLEAR |      /* clear all counters */
0175              V_SPC_CFG_SRC1(1),     /* counter 1 counts cycles */
0176              IOADDR(A_SCD_PERF_CNT_CFG));
0177 #endif
0178     __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
0179     /* Reset the trace buffer */
0180     __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
0181 #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
0182     /* XXXKW may want to expose control to the data-collector */
0183     tb_options |= M_SCD_TRACE_CFG_FORCECNT;
0184 #endif
0185     __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
0186     sbp.tb_armed = 1;
0187 }
0188 
0189 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
0190 {
0191     int i;
0192 
0193     pr_debug(DEVNAME ": tb_intr\n");
0194 
0195     if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
0196         /* XXX should use XKPHYS to make writes bypass L2 */
0197         u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
0198         /* Read out trace */
0199         __raw_writeq(M_SCD_TRACE_CFG_START_READ,
0200                  IOADDR(A_SCD_TRACE_CFG));
0201         __asm__ __volatile__ ("sync" : : : "memory");
0202         /* Loop runs backwards because bundles are read out in reverse order */
0203         for (i = 256 * 6; i > 0; i -= 6) {
0204             /* Subscripts decrease to put bundle in the order */
0205             /*   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
0206             p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
0207             /* read t2 hi */
0208             p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
0209             /* read t2 lo */
0210             p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
0211             /* read t1 hi */
0212             p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
0213             /* read t1 lo */
0214             p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
0215             /* read t0 hi */
0216             p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
0217             /* read t0 lo */
0218         }
0219         if (!sbp.tb_enable) {
0220             pr_debug(DEVNAME ": tb_intr shutdown\n");
0221             __raw_writeq(M_SCD_TRACE_CFG_RESET,
0222                      IOADDR(A_SCD_TRACE_CFG));
0223             sbp.tb_armed = 0;
0224             wake_up_interruptible(&sbp.tb_sync);
0225         } else {
0226             /* knock down current interrupt and get another one later */
0227             arm_tb();
0228         }
0229     } else {
0230         /* No more trace buffer samples */
0231         pr_debug(DEVNAME ": tb_intr full\n");
0232         __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
0233         sbp.tb_armed = 0;
0234         if (!sbp.tb_enable)
0235             wake_up_interruptible(&sbp.tb_sync);
0236         wake_up_interruptible(&sbp.tb_read);
0237     }
0238     return IRQ_HANDLED;
0239 }
0240 
0241 static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
0242 {
0243     printk(DEVNAME ": unexpected pc_intr");
0244     return IRQ_NONE;
0245 }
0246 
0247 /*
0248  * Requires: Already called zclk_timer_init with a value that won't
0249  *       saturate 40 bits.  No subsequent use of SCD performance counters
0250  *       or trace buffer.
0251  */
0252 
0253 static int sbprof_zbprof_start(struct file *filp)
0254 {
0255     u64 scdperfcnt;
0256     int err;
0257 
0258     if (xchg(&sbp.tb_enable, 1))
0259         return -EBUSY;
0260 
0261     pr_debug(DEVNAME ": starting\n");
0262 
0263     sbp.next_tb_sample = 0;
0264     filp->f_pos = 0;
0265 
0266     err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
0267               DEVNAME " trace freeze", &sbp);
0268     if (err)
0269         return -EBUSY;
0270 
0271     /* Make sure there isn't a perf-cnt interrupt waiting */
0272     scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
0273     /* Disable and clear counters, override SRC_1 */
0274     __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
0275              M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
0276              IOADDR(A_SCD_PERF_CNT_CFG));
0277 
0278     /*
0279      * We grab this interrupt to prevent others from trying to use
0280      * it, even though we don't want to service the interrupts
0281      * (they only feed into the trace-on-interrupt mechanism)
0282      */
0283     if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
0284         free_irq(K_INT_TRACE_FREEZE, &sbp);
0285         return -EBUSY;
0286     }
0287 
0288     /*
0289      * I need the core to mask these, but the interrupt mapper to
0290      *  pass them through.  I am exploiting my knowledge that
0291      *  cp0_status masks out IP[5]. krw
0292      */
0293 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
0294     __raw_writeq(K_BCM1480_INT_MAP_I3,
0295              IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +
0296                 ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3)));
0297 #else
0298     __raw_writeq(K_INT_MAP_I3,
0299              IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
0300                 (K_INT_PERF_CNT << 3)));
0301 #endif
0302 
0303     /* Initialize address traps */
0304     __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
0305     __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
0306     __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
0307     __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
0308 
0309     __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
0310     __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
0311     __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
0312     __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
0313 
0314     __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
0315     __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
0316     __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
0317     __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
0318 
0319     /* Initialize Trace Event 0-7 */
0320     /*              when interrupt  */
0321     __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
0322     __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
0323     __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
0324     __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
0325     __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
0326     __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
0327     __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
0328     __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
0329 
0330     /* Initialize Trace Sequence 0-7 */
0331     /*                   Start on event 0 (interrupt) */
0332     __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
0333              IOADDR(A_SCD_TRACE_SEQUENCE_0));
0334     /*            dsamp when d used | asamp when a used */
0335     __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
0336              K_SCD_TRSEQ_TRIGGER_ALL,
0337              IOADDR(A_SCD_TRACE_SEQUENCE_1));
0338     __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
0339     __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
0340     __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
0341     __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
0342     __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
0343     __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
0344 
0345     /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
0346 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
0347     __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f),
0348              IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));
0349 #else
0350     __raw_writeq(1ULL << K_INT_PERF_CNT,
0351              IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
0352 #endif
0353     arm_tb();
0354 
0355     pr_debug(DEVNAME ": done starting\n");
0356 
0357     return 0;
0358 }
0359 
0360 static int sbprof_zbprof_stop(void)
0361 {
0362     int err = 0;
0363 
0364     pr_debug(DEVNAME ": stopping\n");
0365 
0366     if (sbp.tb_enable) {
0367         /*
0368          * XXXKW there is a window here where the intr handler may run,
0369          * see the disable, and do the wake_up before this sleep
0370          * happens.
0371          */
0372         pr_debug(DEVNAME ": wait for disarm\n");
0373         err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed);
0374         pr_debug(DEVNAME ": disarm complete, stat %d\n", err);
0375 
0376         if (err)
0377             return err;
0378 
0379         sbp.tb_enable = 0;
0380         free_irq(K_INT_TRACE_FREEZE, &sbp);
0381         free_irq(K_INT_PERF_CNT, &sbp);
0382     }
0383 
0384     pr_debug(DEVNAME ": done stopping\n");
0385 
0386     return err;
0387 }
0388 
0389 static int sbprof_tb_open(struct inode *inode, struct file *filp)
0390 {
0391     int minor;
0392 
0393     minor = iminor(inode);
0394     if (minor != 0)
0395         return -ENODEV;
0396 
0397     if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED)
0398         return -EBUSY;
0399 
0400     memset(&sbp, 0, sizeof(struct sbprof_tb));
0401     sbp.sbprof_tbbuf = vzalloc(MAX_TBSAMPLE_BYTES);
0402     if (!sbp.sbprof_tbbuf) {
0403         sbp.open = SB_CLOSED;
0404         wmb();
0405         return -ENOMEM;
0406     }
0407 
0408     init_waitqueue_head(&sbp.tb_sync);
0409     init_waitqueue_head(&sbp.tb_read);
0410     mutex_init(&sbp.lock);
0411 
0412     sbp.open = SB_OPEN;
0413     wmb();
0414 
0415     return 0;
0416 }
0417 
0418 static int sbprof_tb_release(struct inode *inode, struct file *filp)
0419 {
0420     int minor;
0421 
0422     minor = iminor(inode);
0423     if (minor != 0 || sbp.open != SB_CLOSED)
0424         return -ENODEV;
0425 
0426     mutex_lock(&sbp.lock);
0427 
0428     if (sbp.tb_armed || sbp.tb_enable)
0429         sbprof_zbprof_stop();
0430 
0431     vfree(sbp.sbprof_tbbuf);
0432     sbp.open = SB_CLOSED;
0433     wmb();
0434 
0435     mutex_unlock(&sbp.lock);
0436 
0437     return 0;
0438 }
0439 
0440 static ssize_t sbprof_tb_read(struct file *filp, char __user *buf,
0441                   size_t size, loff_t *offp)
0442 {
0443     int cur_sample, sample_off, cur_count, sample_left;
0444     char *src;
0445     int   count   =  0;
0446     char __user *dest    =   buf;
0447     long  cur_off = *offp;
0448 
0449     if (!access_ok(buf, size))
0450         return -EFAULT;
0451 
0452     mutex_lock(&sbp.lock);
0453 
0454     count = 0;
0455     cur_sample = cur_off / TB_SAMPLE_SIZE;
0456     sample_off = cur_off % TB_SAMPLE_SIZE;
0457     sample_left = TB_SAMPLE_SIZE - sample_off;
0458 
0459     while (size && (cur_sample < sbp.next_tb_sample)) {
0460         int err;
0461 
0462         cur_count = size < sample_left ? size : sample_left;
0463         src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
0464         err = __copy_to_user(dest, src, cur_count);
0465         if (err) {
0466             *offp = cur_off + cur_count - err;
0467             mutex_unlock(&sbp.lock);
0468             return err;
0469         }
0470         pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
0471              cur_sample, cur_count);
0472         size -= cur_count;
0473         sample_left -= cur_count;
0474         if (!sample_left) {
0475             cur_sample++;
0476             sample_off = 0;
0477             sample_left = TB_SAMPLE_SIZE;
0478         } else {
0479             sample_off += cur_count;
0480         }
0481         cur_off += cur_count;
0482         dest += cur_count;
0483         count += cur_count;
0484     }
0485     *offp = cur_off;
0486     mutex_unlock(&sbp.lock);
0487 
0488     return count;
0489 }
0490 
0491 static long sbprof_tb_ioctl(struct file *filp,
0492                 unsigned int command,
0493                 unsigned long arg)
0494 {
0495     int err = 0;
0496 
0497     switch (command) {
0498     case SBPROF_ZBSTART:
0499         mutex_lock(&sbp.lock);
0500         err = sbprof_zbprof_start(filp);
0501         mutex_unlock(&sbp.lock);
0502         break;
0503 
0504     case SBPROF_ZBSTOP:
0505         mutex_lock(&sbp.lock);
0506         err = sbprof_zbprof_stop();
0507         mutex_unlock(&sbp.lock);
0508         break;
0509 
0510     case SBPROF_ZBWAITFULL: {
0511         err = wait_event_interruptible(sbp.tb_read, TB_FULL);
0512         if (err)
0513             break;
0514 
0515         err = put_user(TB_FULL, (int __user *) arg);
0516         break;
0517     }
0518 
0519     default:
0520         err = -EINVAL;
0521         break;
0522     }
0523 
0524     return err;
0525 }
0526 
0527 static const struct file_operations sbprof_tb_fops = {
0528     .owner      = THIS_MODULE,
0529     .open       = sbprof_tb_open,
0530     .release    = sbprof_tb_release,
0531     .read       = sbprof_tb_read,
0532     .unlocked_ioctl = sbprof_tb_ioctl,
0533     .compat_ioctl   = sbprof_tb_ioctl,
0534     .mmap       = NULL,
0535     .llseek     = default_llseek,
0536 };
0537 
0538 static struct class *tb_class;
0539 static struct device *tb_dev;
0540 
0541 static int __init sbprof_tb_init(void)
0542 {
0543     struct device *dev;
0544     struct class *tbc;
0545     int err;
0546 
0547     if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
0548         printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
0549                SBPROF_TB_MAJOR);
0550         return -EIO;
0551     }
0552 
0553     tbc = class_create(THIS_MODULE, "sb_tracebuffer");
0554     if (IS_ERR(tbc)) {
0555         err = PTR_ERR(tbc);
0556         goto out_chrdev;
0557     }
0558 
0559     tb_class = tbc;
0560 
0561     dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), NULL, "tb");
0562     if (IS_ERR(dev)) {
0563         err = PTR_ERR(dev);
0564         goto out_class;
0565     }
0566     tb_dev = dev;
0567 
0568     sbp.open = SB_CLOSED;
0569     wmb();
0570     tb_period = zbbus_mhz * 10000LL;
0571     pr_info(DEVNAME ": initialized - tb_period = %lld\n",
0572         (long long) tb_period);
0573     return 0;
0574 
0575 out_class:
0576     class_destroy(tb_class);
0577 out_chrdev:
0578     unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
0579 
0580     return err;
0581 }
0582 
0583 static void __exit sbprof_tb_cleanup(void)
0584 {
0585     device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0));
0586     unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
0587     class_destroy(tb_class);
0588 }
0589 
0590 module_init(sbprof_tb_init);
0591 module_exit(sbprof_tb_cleanup);
0592 
0593 MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR);
0594 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
0595 MODULE_LICENSE("GPL");
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