mips/sgi-ip30/ip30-irq.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * ip30-irq.c: Highlevel interrupt handling for IP30 architecture.
0004  */
0005 #include <linux/errno.h>
0006 #include <linux/init.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/irq.h>
0009 #include <linux/irqdomain.h>
0010 #include <linux/percpu.h>
0011 #include <linux/spinlock.h>
0012 #include <linux/tick.h>
0013 #include <linux/types.h>
0014
0015 #include <asm/irq_cpu.h>
0016 #include <asm/sgi/heart.h>
0017
0018 #include "ip30-common.h"
0019
0020 struct heart_irq_data {
0021     u64 *irq_mask;
0022     int cpu;
0023 };
0024
0025 static DECLARE_BITMAP(heart_irq_map, HEART_NUM_IRQS);
0026
0027 static DEFINE_PER_CPU(unsigned long, irq_enable_mask);
0028
0029 static inline int heart_alloc_int(void)
0030 {
0031     int bit;
0032
0033 again:
0034     bit = find_first_zero_bit(heart_irq_map, HEART_NUM_IRQS);
0035     if (bit >= HEART_NUM_IRQS)
0036         return -ENOSPC;
0037
0038     if (test_and_set_bit(bit, heart_irq_map))
0039         goto again;
0040
0041     return bit;
0042 }
0043
0044 static void ip30_error_irq(struct irq_desc *desc)
0045 {
0046     u64 pending, mask, cause, error_irqs, err_reg;
0047     int cpu = smp_processor_id();
0048     int i;
0049
0050     pending = heart_read(&heart_regs->isr);
0051     mask = heart_read(&heart_regs->imr[cpu]);
0052     cause = heart_read(&heart_regs->cause);
0053     error_irqs = (pending & HEART_L4_INT_MASK & mask);
0054
0055     /* Bail if there's nothing to process (how did we get here, then?) */
0056     if (unlikely(!error_irqs))
0057         return;
0058
0059     /* Prevent any of the error IRQs from firing again. */
0060     heart_write(mask & ~(pending), &heart_regs->imr[cpu]);
0061
0062     /* Ack all error IRQs. */
0063     heart_write(HEART_L4_INT_MASK, &heart_regs->clear_isr);
0064
0065     /*
0066      * If we also have a cause value, then something happened, so loop
0067      * through the error IRQs and report a "heart attack" for each one
0068      * and print the value of the HEART cause register.  This is really
0069      * primitive right now, but it should hopefully work until a more
0070      * robust error handling routine can be put together.
0071      *
0072      * Refer to heart.h for the HC_* macros to work out the cause
0073      * that got us here.
0074      */
0075     if (cause) {
0076         pr_alert("IP30: CPU%d: HEART ATTACK! ISR = 0x%.16llx, IMR = 0x%.16llx, CAUSE = 0x%.16llx\n",
0077              cpu, pending, mask, cause);
0078
0079         if (cause & HC_COR_MEM_ERR) {
0080             err_reg = heart_read(&heart_regs->mem_err_addr);
0081             pr_alert("  HEART_MEMERR_ADDR = 0x%.16llx\n", err_reg);
0082         }
0083
0084         /* i = 63; i >= 51; i-- */
0085         for (i = HEART_ERR_MASK_END; i >= HEART_ERR_MASK_START; i--)
0086             if ((pending >> i) & 1)
0087                 pr_alert("  HEART Error IRQ #%d\n", i);
0088
0089         /* XXX: Seems possible to loop forever here, so panic(). */
0090         panic("IP30: Fatal Error !\n");
0091     }
0092
0093     /* Unmask the error IRQs. */
0094     heart_write(mask, &heart_regs->imr[cpu]);
0095 }
0096
0097 static void ip30_normal_irq(struct irq_desc *desc)
0098 {
0099     int cpu = smp_processor_id();
0100     struct irq_domain *domain;
0101     u64 pend, mask;
0102     int ret;
0103
0104     pend = heart_read(&heart_regs->isr);
0105     mask = (heart_read(&heart_regs->imr[cpu]) &
0106         (HEART_L0_INT_MASK | HEART_L1_INT_MASK | HEART_L2_INT_MASK));
0107
0108     pend &= mask;
0109     if (unlikely(!pend))
0110         return;
0111
0112 #ifdef CONFIG_SMP
0113     if (pend & BIT_ULL(HEART_L2_INT_RESCHED_CPU_0)) {
0114         heart_write(BIT_ULL(HEART_L2_INT_RESCHED_CPU_0),
0115                 &heart_regs->clear_isr);
0116         scheduler_ipi();
0117     } else if (pend & BIT_ULL(HEART_L2_INT_RESCHED_CPU_1)) {
0118         heart_write(BIT_ULL(HEART_L2_INT_RESCHED_CPU_1),
0119                 &heart_regs->clear_isr);
0120         scheduler_ipi();
0121     } else if (pend & BIT_ULL(HEART_L2_INT_CALL_CPU_0)) {
0122         heart_write(BIT_ULL(HEART_L2_INT_CALL_CPU_0),
0123                 &heart_regs->clear_isr);
0124         generic_smp_call_function_interrupt();
0125     } else if (pend & BIT_ULL(HEART_L2_INT_CALL_CPU_1)) {
0126         heart_write(BIT_ULL(HEART_L2_INT_CALL_CPU_1),
0127                 &heart_regs->clear_isr);
0128         generic_smp_call_function_interrupt();
0129     } else
0130 #endif
0131     {
0132         domain = irq_desc_get_handler_data(desc);
0133         ret = generic_handle_domain_irq(domain, __ffs(pend));
0134         if (ret)
0135             spurious_interrupt();
0136     }
0137 }
0138
0139 static void ip30_ack_heart_irq(struct irq_data *d)
0140 {
0141     heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr);
0142 }
0143
0144 static void ip30_mask_heart_irq(struct irq_data *d)
0145 {
0146     struct heart_irq_data *hd = irq_data_get_irq_chip_data(d);
0147     unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);
0148
0149     clear_bit(d->hwirq, mask);
0150     heart_write(*mask, &heart_regs->imr[hd->cpu]);
0151 }
0152
0153 static void ip30_mask_and_ack_heart_irq(struct irq_data *d)
0154 {
0155     struct heart_irq_data *hd = irq_data_get_irq_chip_data(d);
0156     unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);
0157
0158     clear_bit(d->hwirq, mask);
0159     heart_write(*mask, &heart_regs->imr[hd->cpu]);
0160     heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr);
0161 }
0162
0163 static void ip30_unmask_heart_irq(struct irq_data *d)
0164 {
0165     struct heart_irq_data *hd = irq_data_get_irq_chip_data(d);
0166     unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);
0167
0168     set_bit(d->hwirq, mask);
0169     heart_write(*mask, &heart_regs->imr[hd->cpu]);
0170 }
0171
0172 static int ip30_set_heart_irq_affinity(struct irq_data *d,
0173                        const struct cpumask *mask, bool force)
0174 {
0175     struct heart_irq_data *hd = irq_data_get_irq_chip_data(d);
0176
0177     if (!hd)
0178         return -EINVAL;
0179
0180     if (irqd_is_started(d))
0181         ip30_mask_and_ack_heart_irq(d);
0182
0183     hd->cpu = cpumask_first_and(mask, cpu_online_mask);
0184
0185     if (irqd_is_started(d))
0186         ip30_unmask_heart_irq(d);
0187
0188     irq_data_update_effective_affinity(d, cpumask_of(hd->cpu));
0189
0190     return 0;
0191 }
0192
0193 static struct irq_chip heart_irq_chip = {
0194     .name           = "HEART",
0195     .irq_ack        = ip30_ack_heart_irq,
0196     .irq_mask       = ip30_mask_heart_irq,
0197     .irq_mask_ack       = ip30_mask_and_ack_heart_irq,
0198     .irq_unmask     = ip30_unmask_heart_irq,
0199     .irq_set_affinity   = ip30_set_heart_irq_affinity,
0200 };
0201
0202 static int heart_domain_alloc(struct irq_domain *domain, unsigned int virq,
0203                   unsigned int nr_irqs, void *arg)
0204 {
0205     struct irq_alloc_info *info = arg;
0206     struct heart_irq_data *hd;
0207     int hwirq;
0208
0209     if (nr_irqs > 1 || !info)
0210         return -EINVAL;
0211
0212     hd = kzalloc(sizeof(*hd), GFP_KERNEL);
0213     if (!hd)
0214         return -ENOMEM;
0215
0216     hwirq = heart_alloc_int();
0217     if (hwirq < 0) {
0218         kfree(hd);
0219         return -EAGAIN;
0220     }
0221     irq_domain_set_info(domain, virq, hwirq, &heart_irq_chip, hd,
0222                 handle_level_irq, NULL, NULL);
0223
0224     return 0;
0225 }
0226
0227 static void heart_domain_free(struct irq_domain *domain,
0228                   unsigned int virq, unsigned int nr_irqs)
0229 {
0230     struct irq_data *irqd;
0231
0232     if (nr_irqs > 1)
0233         return;
0234
0235     irqd = irq_domain_get_irq_data(domain, virq);
0236     if (irqd) {
0237         clear_bit(irqd->hwirq, heart_irq_map);
0238         kfree(irqd->chip_data);
0239     }
0240 }
0241
0242 static const struct irq_domain_ops heart_domain_ops = {
0243     .alloc = heart_domain_alloc,
0244     .free  = heart_domain_free,
0245 };
0246
0247 void __init ip30_install_ipi(void)
0248 {
0249     int cpu = smp_processor_id();
0250     unsigned long *mask = &per_cpu(irq_enable_mask, cpu);
0251
0252     set_bit(HEART_L2_INT_RESCHED_CPU_0 + cpu, mask);
0253     heart_write(BIT_ULL(HEART_L2_INT_RESCHED_CPU_0 + cpu),
0254             &heart_regs->clear_isr);
0255     set_bit(HEART_L2_INT_CALL_CPU_0 + cpu, mask);
0256     heart_write(BIT_ULL(HEART_L2_INT_CALL_CPU_0 + cpu),
0257             &heart_regs->clear_isr);
0258
0259     heart_write(*mask, &heart_regs->imr[cpu]);
0260 }
0261
0262 void __init arch_init_irq(void)
0263 {
0264     struct irq_domain *domain;
0265     struct fwnode_handle *fn;
0266     unsigned long *mask;
0267     int i;
0268
0269     mips_cpu_irq_init();
0270
0271     /* Mask all IRQs. */
0272     heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[0]);
0273     heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[1]);
0274     heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[2]);
0275     heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[3]);
0276
0277     /* Ack everything. */
0278     heart_write(HEART_ACK_ALL_MASK, &heart_regs->clear_isr);
0279
0280     /* Enable specific HEART error IRQs for each CPU. */
0281     mask = &per_cpu(irq_enable_mask, 0);
0282     *mask |= HEART_CPU0_ERR_MASK;
0283     heart_write(*mask, &heart_regs->imr[0]);
0284     mask = &per_cpu(irq_enable_mask, 1);
0285     *mask |= HEART_CPU1_ERR_MASK;
0286     heart_write(*mask, &heart_regs->imr[1]);
0287
0288     /*
0289      * Some HEART bits are reserved by hardware or by software convention.
0290      * Mark these as reserved right away so they won't be accidentally
0291      * used later.
0292      */
0293     set_bit(HEART_L0_INT_GENERIC, heart_irq_map);
0294     set_bit(HEART_L0_INT_FLOW_CTRL_HWTR_0, heart_irq_map);
0295     set_bit(HEART_L0_INT_FLOW_CTRL_HWTR_1, heart_irq_map);
0296     set_bit(HEART_L2_INT_RESCHED_CPU_0, heart_irq_map);
0297     set_bit(HEART_L2_INT_RESCHED_CPU_1, heart_irq_map);
0298     set_bit(HEART_L2_INT_CALL_CPU_0, heart_irq_map);
0299     set_bit(HEART_L2_INT_CALL_CPU_1, heart_irq_map);
0300     set_bit(HEART_L3_INT_TIMER, heart_irq_map);
0301
0302     /* Reserve the error interrupts (#51 to #63). */
0303     for (i = HEART_L4_INT_XWID_ERR_9; i <= HEART_L4_INT_HEART_EXCP; i++)
0304         set_bit(i, heart_irq_map);
0305
0306     fn = irq_domain_alloc_named_fwnode("HEART");
0307     WARN_ON(fn == NULL);
0308     if (!fn)
0309         return;
0310     domain = irq_domain_create_linear(fn, HEART_NUM_IRQS,
0311                       &heart_domain_ops, NULL);
0312     WARN_ON(domain == NULL);
0313     if (!domain)
0314         return;
0315
0316     irq_set_default_host(domain);
0317
0318     irq_set_percpu_devid(IP30_HEART_L0_IRQ);
0319     irq_set_chained_handler_and_data(IP30_HEART_L0_IRQ, ip30_normal_irq,
0320                      domain);
0321     irq_set_percpu_devid(IP30_HEART_L1_IRQ);
0322     irq_set_chained_handler_and_data(IP30_HEART_L1_IRQ, ip30_normal_irq,
0323                      domain);
0324     irq_set_percpu_devid(IP30_HEART_L2_IRQ);
0325     irq_set_chained_handler_and_data(IP30_HEART_L2_IRQ, ip30_normal_irq,
0326                      domain);
0327     irq_set_percpu_devid(IP30_HEART_ERR_IRQ);
0328     irq_set_chained_handler_and_data(IP30_HEART_ERR_IRQ, ip30_error_irq,
0329                      domain);
0330 }