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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 
0003 #ifndef __IP30_COMMON_H
0004 #define __IP30_COMMON_H
0005 
0006 /*
0007  * Power Switch is wired via BaseIO BRIDGE slot #6.
0008  *
0009  * ACFail is wired via BaseIO BRIDGE slot #7.
0010  */
0011 #define IP30_POWER_IRQ      HEART_L2_INT_POWER_BTN
0012 
0013 #define IP30_HEART_L0_IRQ   (MIPS_CPU_IRQ_BASE + 2)
0014 #define IP30_HEART_L1_IRQ   (MIPS_CPU_IRQ_BASE + 3)
0015 #define IP30_HEART_L2_IRQ   (MIPS_CPU_IRQ_BASE + 4)
0016 #define IP30_HEART_TIMER_IRQ    (MIPS_CPU_IRQ_BASE + 5)
0017 #define IP30_HEART_ERR_IRQ  (MIPS_CPU_IRQ_BASE + 6)
0018 
0019 extern void __init ip30_install_ipi(void);
0020 extern struct plat_smp_ops ip30_smp_ops;
0021 extern void __init ip30_per_cpu_init(void);
0022 
0023 #endif /* __IP30_COMMON_H */