mips/sgi-ip22/ip22-time.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Time operations for IP22 machines. Original code may come from
0007  * Ralf Baechle or David S. Miller (sorry guys, i'm really not sure)
0008  *
0009  * Copyright (C) 2001 by Ladislav Michl
0010  * Copyright (C) 2003, 06 Ralf Baechle (ralf@linux-mips.org)
0011  */
0012 #include <linux/bcd.h>
0013 #include <linux/i8253.h>
0014 #include <linux/init.h>
0015 #include <linux/irq.h>
0016 #include <linux/kernel.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/kernel_stat.h>
0019 #include <linux/time.h>
0020 #include <linux/ftrace.h>
0021
0022 #include <asm/cpu.h>
0023 #include <asm/mipsregs.h>
0024 #include <asm/io.h>
0025 #include <asm/irq.h>
0026 #include <asm/time.h>
0027 #include <asm/sgialib.h>
0028 #include <asm/sgi/ioc.h>
0029 #include <asm/sgi/hpc3.h>
0030 #include <asm/sgi/ip22.h>
0031
0032 static unsigned long dosample(void)
0033 {
0034     u32 ct0, ct1;
0035     u8 msb;
0036
0037     /* Start the counter. */
0038     sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
0039              SGINT_TCWORD_MRGEN);
0040     sgint->tcnt2 = SGINT_TCSAMP_COUNTER & 0xff;
0041     sgint->tcnt2 = SGINT_TCSAMP_COUNTER >> 8;
0042
0043     /* Get initial counter invariant */
0044     ct0 = read_c0_count();
0045
0046     /* Latch and spin until top byte of counter2 is zero */
0047     do {
0048         writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword);
0049         (void) readb(&sgint->tcnt2);
0050         msb = readb(&sgint->tcnt2);
0051         ct1 = read_c0_count();
0052     } while (msb);
0053
0054     /* Stop the counter. */
0055     writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MSWST,
0056            &sgint->tcword);
0057     /*
0058      * Return the difference, this is how far the r4k counter increments
0059      * for every 1/HZ seconds. We round off the nearest 1 MHz of master
0060      * clock (= 1000000 / HZ / 2).
0061      */
0062
0063     return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
0064 }
0065
0066 /*
0067  * Here we need to calibrate the cycle counter to at least be close.
0068  */
0069 __init void plat_time_init(void)
0070 {
0071     unsigned long r4k_ticks[3];
0072     unsigned long r4k_tick;
0073
0074     /*
0075      * Figure out the r4k offset, the algorithm is very simple and works in
0076      * _all_ cases as long as the 8254 counter register itself works ok (as
0077      * an interrupt driving timer it does not because of bug, this is why
0078      * we are using the onchip r4k counter/compare register to serve this
0079      * purpose, but for r4k_offset calculation it will work ok for us).
0080      * There are other very complicated ways of performing this calculation
0081      * but this one works just fine so I am not going to futz around. ;-)
0082      */
0083     printk(KERN_INFO "Calibrating system timer... ");
0084     dosample(); /* Prime cache. */
0085     dosample(); /* Prime cache. */
0086     /* Zero is NOT an option. */
0087     do {
0088         r4k_ticks[0] = dosample();
0089     } while (!r4k_ticks[0]);
0090     do {
0091         r4k_ticks[1] = dosample();
0092     } while (!r4k_ticks[1]);
0093
0094     if (r4k_ticks[0] != r4k_ticks[1]) {
0095         printk("warning: timer counts differ, retrying... ");
0096         r4k_ticks[2] = dosample();
0097         if (r4k_ticks[2] == r4k_ticks[0]
0098             || r4k_ticks[2] == r4k_ticks[1])
0099             r4k_tick = r4k_ticks[2];
0100         else {
0101             printk("disagreement, using average... ");
0102             r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
0103                    + r4k_ticks[2]) / 3;
0104         }
0105     } else
0106         r4k_tick = r4k_ticks[0];
0107
0108     printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
0109         (int) (r4k_tick / (500000 / HZ)),
0110         (int) (r4k_tick % (500000 / HZ)));
0111
0112     mips_hpt_frequency = r4k_tick * HZ;
0113
0114     if (ip22_is_fullhouse())
0115         setup_pit_timer();
0116 }
0117
0118 /* Generic SGI handler for (spurious) 8254 interrupts */
0119 void __irq_entry indy_8254timer_irq(void)
0120 {
0121     int irq = SGI_8254_0_IRQ;
0122     ULONG cnt;
0123     char c;
0124
0125     irq_enter();
0126     kstat_incr_irq_this_cpu(irq);
0127     printk(KERN_ALERT "Oops, got 8254 interrupt.\n");
0128     ArcRead(0, &c, 1, &cnt);
0129     ArcEnterInteractiveMode();
0130     irq_exit();
0131 }