mips/sgi-ip22/ip22-mc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * ip22-mc.c: Routines for manipulating SGI Memory Controller.
0004  *
0005  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
0006  * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
0007  * Copyright (C) 2003 Ladislav Michl  (ladis@linux-mips.org)
0008  * Copyright (C) 2004 Peter Fuerst    (pf@net.alphadv.de) - IP28
0009  */
0010
0011 #include <linux/init.h>
0012 #include <linux/export.h>
0013 #include <linux/kernel.h>
0014 #include <linux/memblock.h>
0015 #include <linux/spinlock.h>
0016
0017 #include <asm/io.h>
0018 #include <asm/bootinfo.h>
0019 #include <asm/sgialib.h>
0020 #include <asm/sgi/mc.h>
0021 #include <asm/sgi/hpc3.h>
0022 #include <asm/sgi/ip22.h>
0023
0024 struct sgimc_regs *sgimc;
0025
0026 EXPORT_SYMBOL(sgimc);
0027
0028 static inline unsigned long get_bank_addr(unsigned int memconfig)
0029 {
0030     return (memconfig & SGIMC_MCONFIG_BASEADDR) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22);
0031 }
0032
0033 static inline unsigned long get_bank_size(unsigned int memconfig)
0034 {
0035     return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
0036 }
0037
0038 static inline unsigned int get_bank_config(int bank)
0039 {
0040     unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
0041     return bank % 2 ? res & 0xffff : res >> 16;
0042 }
0043
0044 #if defined(CONFIG_SGI_IP28) || defined(CONFIG_32BIT)
0045 static void __init probe_memory(void)
0046 {
0047     /* prom detects all usable memory */
0048 }
0049 #else
0050 /*
0051  * Detect installed memory, which PROM misses
0052  */
0053 static void __init probe_memory(void)
0054 {
0055     unsigned long addr, size;
0056     int i;
0057
0058     printk(KERN_INFO "MC: Probing memory configuration:\n");
0059     for (i = 0; i < 4; i++) {
0060         unsigned int tmp = get_bank_config(i);
0061         if (!(tmp & SGIMC_MCONFIG_BVALID))
0062             continue;
0063
0064         size = get_bank_size(tmp);
0065         addr = get_bank_addr(tmp);
0066         printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
0067             i, size / 1024 / 1024, addr);
0068
0069         if (addr >= SGIMC_SEG1_BADDR)
0070             memblock_add(addr, size);
0071     }
0072 }
0073 #endif
0074
0075 void __init sgimc_init(void)
0076 {
0077     u32 tmp;
0078
0079     /* ioremap can't fail */
0080     sgimc = (struct sgimc_regs *)
0081         ioremap(SGIMC_BASE, sizeof(struct sgimc_regs));
0082
0083     printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
0084            (int) sgimc->systemid & SGIMC_SYSID_MASKREV);
0085
0086     /* Place the MC into a known state.  This must be done before
0087      * interrupts are first enabled etc.
0088      */
0089
0090     /* Step 0: Make sure we turn off the watchdog in case it's
0091      *     still running (which might be the case after a
0092      *     soft reboot).
0093      */
0094     tmp = sgimc->cpuctrl0;
0095     tmp &= ~SGIMC_CCTRL0_WDOG;
0096     sgimc->cpuctrl0 = tmp;
0097
0098     /* Step 1: The CPU/GIO error status registers will not latch
0099      *     up a new error status until the register has been
0100      *     cleared by the cpu.  These status registers are
0101      *     cleared by writing any value to them.
0102      */
0103     sgimc->cstat = sgimc->gstat = 0;
0104
0105     /* Step 2: Enable all parity checking in cpu control register
0106      *     zero.
0107      */
0108     /* don't touch parity settings for IP28 */
0109     tmp = sgimc->cpuctrl0;
0110 #ifndef CONFIG_SGI_IP28
0111     tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM;
0112 #endif
0113     tmp |= SGIMC_CCTRL0_R4KNOCHKPARR;
0114     sgimc->cpuctrl0 = tmp;
0115
0116     /* Step 3: Setup the MC write buffer depth, this is controlled
0117      *     in cpu control register 1 in the lower 4 bits.
0118      */
0119     tmp = sgimc->cpuctrl1;
0120     tmp &= ~0xf;
0121     tmp |= 0xd;
0122     sgimc->cpuctrl1 = tmp;
0123
0124     /* Step 4: Initialize the RPSS divider register to run as fast
0125      *     as it can correctly operate.  The register is laid
0126      *     out as follows:
0127      *
0128      *     ----------------------------------------
0129      *     |  RESERVED  |   INCREMENT   | DIVIDER |
0130      *     ----------------------------------------
0131      *      31        16 15        8 7   0
0132      *
0133      *     DIVIDER determines how often a 'tick' happens,
0134      *     INCREMENT determines by how the RPSS increment
0135      *     registers value increases at each 'tick'. Thus,
0136      *     for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
0137      */
0138     sgimc->divider = 0x101;
0139
0140     /* Step 5: Initialize GIO64 arbitrator configuration register.
0141      *
0142      * NOTE: HPC init code in sgihpc_init() must run before us because
0143      *   we need to know Guiness vs. FullHouse and the board
0144      *   revision on this machine. You have been warned.
0145      */
0146
0147     /* First the basic invariants across all GIO64 implementations. */
0148     tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */
0149     tmp |= SGIMC_GIOPAR_HPC64;  /* All 1st HPC's interface at 64bits */
0150     tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */
0151
0152     if (ip22_is_fullhouse()) {
0153         /* Fullhouse specific settings. */
0154         if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
0155             tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */
0156             tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp0 pipelines */
0157             tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
0158             tmp |= SGIMC_GIOPAR_RTIMEEXP0;  /* exp0 is realtime */
0159         } else {
0160             tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */
0161             tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp[01] pipelined */
0162             tmp |= SGIMC_GIOPAR_PLINEEXP1;
0163             tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
0164         }
0165     } else {
0166         /* Guiness specific settings. */
0167         tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */
0168         tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
0169     }
0170     sgimc->giopar = tmp;    /* poof */
0171
0172     probe_memory();
0173 }
0174
0175 #ifdef CONFIG_SGI_IP28
0176 void __init prom_cleanup(void)
0177 {
0178     u32 mconfig1;
0179     unsigned long flags;
0180     spinlock_t lock;
0181
0182     /*
0183      * because ARCS accesses memory uncached we wait until ARCS
0184      * isn't needed any longer, before we switch from slow to
0185      * normal mode
0186      */
0187     spin_lock_irqsave(&lock, flags);
0188     mconfig1 = sgimc->mconfig1;
0189     /* map ECC register */
0190     sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060;
0191     iob();
0192     /* switch to normal mode */
0193     *(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;
0194     iob();
0195     /* reduce WR_COL */
0196     sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4;
0197     iob();
0198     /* restore old config */
0199     sgimc->mconfig1 = mconfig1;
0200     iob();
0201     spin_unlock_irqrestore(&lock, flags);
0202 }
0203 #endif