mips/rb532/irq.c

0001 /*
0002  *  This program is free software; you can redistribute  it and/or modify it
0003  *  under  the terms of  the GNU General  Public License as published by the
0004  *  Free Software Foundation;  either version 2 of the  License, or (at your
0005  *  option) any later version.
0006  *
0007  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0008  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0009  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0010  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0011  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0012  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0013  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0014  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0015  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0016  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0017  *
0018  *  You should have received a copy of the  GNU General Public License along
0019  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0020  *  675 Mass Ave, Cambridge, MA 02139, USA.
0021  *
0022  * Copyright 2002 MontaVista Software Inc.
0023  * Author: MontaVista Software, Inc.
0024  *      stevel@mvista.com or source@mvista.com
0025  */
0026
0027 #include <linux/bitops.h>
0028 #include <linux/errno.h>
0029 #include <linux/init.h>
0030 #include <linux/io.h>
0031 #include <linux/kernel_stat.h>
0032 #include <linux/signal.h>
0033 #include <linux/sched.h>
0034 #include <linux/types.h>
0035 #include <linux/interrupt.h>
0036 #include <linux/ioport.h>
0037 #include <linux/timex.h>
0038 #include <linux/random.h>
0039 #include <linux/delay.h>
0040
0041 #include <asm/bootinfo.h>
0042 #include <asm/time.h>
0043 #include <asm/mipsregs.h>
0044
0045 #include <asm/mach-rc32434/irq.h>
0046 #include <asm/mach-rc32434/gpio.h>
0047
0048 struct intr_group {
0049     u32 mask;   /* mask of valid bits in pending/mask registers */
0050     volatile u32 *base_addr;
0051 };
0052
0053 #define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
0054
0055 #if (NR_IRQS < RC32434_NR_IRQS)
0056 #error Too little irqs defined. Did you override <asm/irq.h> ?
0057 #endif
0058
0059 static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
0060     {
0061         .mask   = 0x0000efff,
0062         .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
0063     {
0064         .mask   = 0x00001fff,
0065         .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
0066     {
0067         .mask   = 0x00000007,
0068         .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
0069     {
0070         .mask   = 0x0003ffff,
0071         .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
0072     {
0073         .mask   = 0xffffffff,
0074         .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
0075 };
0076
0077 #define READ_PEND(base) (*(base))
0078 #define READ_MASK(base) (*(base + 2))
0079 #define WRITE_MASK(base, val) (*(base + 2) = (val))
0080
0081 static inline int irq_to_group(unsigned int irq_nr)
0082 {
0083     return (irq_nr - GROUP0_IRQ_BASE) >> 5;
0084 }
0085
0086 static inline int group_to_ip(unsigned int group)
0087 {
0088     return group + 2;
0089 }
0090
0091 static inline void enable_local_irq(unsigned int ip)
0092 {
0093     int ipnum = 0x100 << ip;
0094
0095     set_c0_status(ipnum);
0096 }
0097
0098 static inline void disable_local_irq(unsigned int ip)
0099 {
0100     int ipnum = 0x100 << ip;
0101
0102     clear_c0_status(ipnum);
0103 }
0104
0105 static inline void ack_local_irq(unsigned int ip)
0106 {
0107     int ipnum = 0x100 << ip;
0108
0109     clear_c0_cause(ipnum);
0110 }
0111
0112 static void rb532_enable_irq(struct irq_data *d)
0113 {
0114     unsigned int group, intr_bit, irq_nr = d->irq;
0115     int ip = irq_nr - GROUP0_IRQ_BASE;
0116     volatile unsigned int *addr;
0117
0118     if (ip < 0)
0119         enable_local_irq(irq_nr);
0120     else {
0121         group = ip >> 5;
0122
0123         ip &= (1 << 5) - 1;
0124         intr_bit = 1 << ip;
0125
0126         enable_local_irq(group_to_ip(group));
0127
0128         addr = intr_group[group].base_addr;
0129         WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
0130     }
0131 }
0132
0133 static void rb532_disable_irq(struct irq_data *d)
0134 {
0135     unsigned int group, intr_bit, mask, irq_nr = d->irq;
0136     int ip = irq_nr - GROUP0_IRQ_BASE;
0137     volatile unsigned int *addr;
0138
0139     if (ip < 0) {
0140         disable_local_irq(irq_nr);
0141     } else {
0142         group = ip >> 5;
0143
0144         ip &= (1 << 5) - 1;
0145         intr_bit = 1 << ip;
0146         addr = intr_group[group].base_addr;
0147         mask = READ_MASK(addr);
0148         mask |= intr_bit;
0149         WRITE_MASK(addr, mask);
0150
0151         /* There is a maximum of 14 GPIO interrupts */
0152         if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
0153             rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
0154
0155         /*
0156          * if there are no more interrupts enabled in this
0157          * group, disable corresponding IP
0158          */
0159         if (mask == intr_group[group].mask)
0160             disable_local_irq(group_to_ip(group));
0161     }
0162 }
0163
0164 static void rb532_mask_and_ack_irq(struct irq_data *d)
0165 {
0166     rb532_disable_irq(d);
0167     ack_local_irq(group_to_ip(irq_to_group(d->irq)));
0168 }
0169
0170 static int rb532_set_type(struct irq_data *d,  unsigned type)
0171 {
0172     int gpio = d->irq - GPIO_MAPPED_IRQ_BASE;
0173     int group = irq_to_group(d->irq);
0174
0175     if (group != GPIO_MAPPED_IRQ_GROUP || d->irq > (GROUP4_IRQ_BASE + 13))
0176         return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
0177
0178     switch (type) {
0179     case IRQ_TYPE_LEVEL_HIGH:
0180         rb532_gpio_set_ilevel(1, gpio);
0181         break;
0182     case IRQ_TYPE_LEVEL_LOW:
0183         rb532_gpio_set_ilevel(0, gpio);
0184         break;
0185     default:
0186         return -EINVAL;
0187     }
0188
0189     return 0;
0190 }
0191
0192 static struct irq_chip rc32434_irq_type = {
0193     .name       = "RB532",
0194     .irq_ack    = rb532_disable_irq,
0195     .irq_mask   = rb532_disable_irq,
0196     .irq_mask_ack   = rb532_mask_and_ack_irq,
0197     .irq_unmask = rb532_enable_irq,
0198     .irq_set_type   = rb532_set_type,
0199 };
0200
0201 void __init arch_init_irq(void)
0202 {
0203     int i;
0204
0205     pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
0206
0207     for (i = 0; i < RC32434_NR_IRQS; i++)
0208         irq_set_chip_and_handler(i, &rc32434_irq_type,
0209                      handle_level_irq);
0210 }
0211
0212 /* Main Interrupt dispatcher */
0213 asmlinkage void plat_irq_dispatch(void)
0214 {
0215     unsigned int ip, pend, group;
0216     volatile unsigned int *addr;
0217     unsigned int cp0_cause = read_c0_cause() & read_c0_status();
0218
0219     if (cp0_cause & CAUSEF_IP7) {
0220         do_IRQ(7);
0221     } else {
0222         ip = (cp0_cause & 0x7c00);
0223         if (ip) {
0224             group = 21 + (fls(ip) - 32);
0225
0226             addr = intr_group[group].base_addr;
0227
0228             pend = READ_PEND(addr);
0229             pend &= ~READ_MASK(addr);   /* only unmasked interrupts */
0230             pend = 39 + (fls(pend) - 32);
0231             do_IRQ((group << 5) + pend);
0232         }
0233     }
0234 }