mips/rb532/devices.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  RouterBoard 500 Platform devices
0004  *
0005  *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
0006  *  Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
0007  */
0008 #include <linux/kernel.h>
0009 #include <linux/export.h>
0010 #include <linux/init.h>
0011 #include <linux/ctype.h>
0012 #include <linux/string.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/mtd/platnand.h>
0015 #include <linux/mtd/mtd.h>
0016 #include <linux/gpio.h>
0017 #include <linux/gpio/machine.h>
0018 #include <linux/gpio_keys.h>
0019 #include <linux/input.h>
0020 #include <linux/serial_8250.h>
0021
0022 #include <asm/bootinfo.h>
0023
0024 #include <asm/mach-rc32434/rc32434.h>
0025 #include <asm/mach-rc32434/dma.h>
0026 #include <asm/mach-rc32434/dma_v.h>
0027 #include <asm/mach-rc32434/eth.h>
0028 #include <asm/mach-rc32434/rb.h>
0029 #include <asm/mach-rc32434/integ.h>
0030 #include <asm/mach-rc32434/gpio.h>
0031 #include <asm/mach-rc32434/irq.h>
0032
0033 #define ETH0_RX_DMA_ADDR  (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
0034 #define ETH0_TX_DMA_ADDR  (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
0035
0036 extern unsigned int idt_cpu_freq;
0037
0038 static struct mpmc_device dev3;
0039
0040 void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
0041 {
0042     unsigned long flags;
0043
0044     spin_lock_irqsave(&dev3.lock, flags);
0045
0046     dev3.state = (dev3.state | or_mask) & ~nand_mask;
0047     writeb(dev3.state, dev3.base);
0048
0049     spin_unlock_irqrestore(&dev3.lock, flags);
0050 }
0051 EXPORT_SYMBOL(set_latch_u5);
0052
0053 unsigned char get_latch_u5(void)
0054 {
0055     return dev3.state;
0056 }
0057 EXPORT_SYMBOL(get_latch_u5);
0058
0059 static struct resource korina_dev0_res[] = {
0060     {
0061         .name = "emac",
0062         .start = ETH0_BASE_ADDR,
0063         .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
0064         .flags = IORESOURCE_MEM,
0065      }, {
0066         .name = "rx",
0067         .start = ETH0_DMA_RX_IRQ,
0068         .end = ETH0_DMA_RX_IRQ,
0069         .flags = IORESOURCE_IRQ
0070     }, {
0071         .name = "tx",
0072         .start = ETH0_DMA_TX_IRQ,
0073         .end = ETH0_DMA_TX_IRQ,
0074         .flags = IORESOURCE_IRQ
0075     }, {
0076         .name = "dma_rx",
0077         .start = ETH0_RX_DMA_ADDR,
0078         .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
0079         .flags = IORESOURCE_MEM,
0080      }, {
0081         .name = "dma_tx",
0082         .start = ETH0_TX_DMA_ADDR,
0083         .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
0084         .flags = IORESOURCE_MEM,
0085      }
0086 };
0087
0088 static struct korina_device korina_dev0_data = {
0089     .name = "korina0",
0090     .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
0091 };
0092
0093 static struct platform_device korina_dev0 = {
0094     .id = -1,
0095     .name = "korina",
0096     .resource = korina_dev0_res,
0097     .num_resources = ARRAY_SIZE(korina_dev0_res),
0098     .dev = {
0099         .platform_data = &korina_dev0_data.mac,
0100     }
0101 };
0102
0103 static struct resource cf_slot0_res[] = {
0104     {
0105         .name = "cf_membase",
0106         .flags = IORESOURCE_MEM
0107     }, {
0108         .name = "cf_irq",
0109         .start = (8 + 4 * 32 + CF_GPIO_NUM),    /* 149 */
0110         .end = (8 + 4 * 32 + CF_GPIO_NUM),
0111         .flags = IORESOURCE_IRQ
0112     }
0113 };
0114
0115 static struct gpiod_lookup_table cf_slot0_gpio_table = {
0116     .dev_id = "pata-rb532-cf",
0117     .table = {
0118         GPIO_LOOKUP("gpio0", CF_GPIO_NUM,
0119                 NULL, GPIO_ACTIVE_HIGH),
0120         { },
0121     },
0122 };
0123
0124 static struct platform_device cf_slot0 = {
0125     .id = -1,
0126     .name = "pata-rb532-cf",
0127     .resource = cf_slot0_res,
0128     .num_resources = ARRAY_SIZE(cf_slot0_res),
0129 };
0130
0131 /* Resources and device for NAND */
0132 static int rb532_dev_ready(struct nand_chip *chip)
0133 {
0134     return gpio_get_value(GPIO_RDY);
0135 }
0136
0137 static void rb532_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
0138 {
0139     unsigned char orbits, nandbits;
0140
0141     if (ctrl & NAND_CTRL_CHANGE) {
0142         orbits = (ctrl & NAND_CLE) << 1;
0143         orbits |= (ctrl & NAND_ALE) >> 1;
0144
0145         nandbits = (~ctrl & NAND_CLE) << 1;
0146         nandbits |= (~ctrl & NAND_ALE) >> 1;
0147
0148         set_latch_u5(orbits, nandbits);
0149     }
0150     if (cmd != NAND_CMD_NONE)
0151         writeb(cmd, chip->legacy.IO_ADDR_W);
0152 }
0153
0154 static struct resource nand_slot0_res[] = {
0155     [0] = {
0156         .name = "nand_membase",
0157         .flags = IORESOURCE_MEM
0158     }
0159 };
0160
0161 static struct platform_nand_data rb532_nand_data = {
0162     .ctrl.dev_ready = rb532_dev_ready,
0163     .ctrl.cmd_ctrl  = rb532_cmd_ctrl,
0164 };
0165
0166 static struct platform_device nand_slot0 = {
0167     .name = "gen_nand",
0168     .id = -1,
0169     .resource = nand_slot0_res,
0170     .num_resources = ARRAY_SIZE(nand_slot0_res),
0171     .dev.platform_data = &rb532_nand_data,
0172 };
0173
0174 static struct mtd_partition rb532_partition_info[] = {
0175     {
0176         .name = "Routerboard NAND boot",
0177         .offset = 0,
0178         .size = 4 * 1024 * 1024,
0179     }, {
0180         .name = "rootfs",
0181         .offset = MTDPART_OFS_NXTBLK,
0182         .size = MTDPART_SIZ_FULL,
0183     }
0184 };
0185
0186 static struct platform_device rb532_led = {
0187     .name = "rb532-led",
0188     .id = -1,
0189 };
0190
0191 static struct platform_device rb532_button = {
0192     .name   = "rb532-button",
0193     .id = -1,
0194 };
0195
0196 static struct resource rb532_wdt_res[] = {
0197     {
0198         .name = "rb532_wdt_res",
0199         .start = INTEG0_BASE_ADDR,
0200         .end = INTEG0_BASE_ADDR + sizeof(struct integ),
0201         .flags = IORESOURCE_MEM,
0202     }
0203 };
0204
0205 static struct platform_device rb532_wdt = {
0206     .name       = "rc32434_wdt",
0207     .id     = -1,
0208     .resource   = rb532_wdt_res,
0209     .num_resources  = ARRAY_SIZE(rb532_wdt_res),
0210 };
0211
0212 static struct plat_serial8250_port rb532_uart_res[] = {
0213     {
0214         .type           = PORT_16550A,
0215         .membase    = (char *)KSEG1ADDR(REGBASE + UART0BASE),
0216         .irq        = UART0_IRQ,
0217         .regshift   = 2,
0218         .iotype     = UPIO_MEM,
0219         .flags      = UPF_BOOT_AUTOCONF,
0220     },
0221     {
0222         .flags      = 0,
0223     }
0224 };
0225
0226 static struct platform_device rb532_uart = {
0227     .name          = "serial8250",
0228     .id        = PLAT8250_DEV_PLATFORM,
0229     .dev.platform_data = &rb532_uart_res,
0230 };
0231
0232 static struct platform_device *rb532_devs[] = {
0233     &korina_dev0,
0234     &nand_slot0,
0235     &cf_slot0,
0236     &rb532_led,
0237     &rb532_button,
0238     &rb532_uart,
0239     &rb532_wdt
0240 };
0241
0242 /* NAND definitions */
0243 #define NAND_CHIP_DELAY 25
0244
0245 static void __init rb532_nand_setup(void)
0246 {
0247     switch (mips_machtype) {
0248     case MACH_MIKROTIK_RB532A:
0249         set_latch_u5(LO_FOFF | LO_CEX,
0250                 LO_ULED | LO_ALE | LO_CLE | LO_WPX);
0251         break;
0252     default:
0253         set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
0254                 LO_ULED | LO_ALE | LO_CLE);
0255         break;
0256     }
0257
0258     /* Setup NAND specific settings */
0259     rb532_nand_data.chip.nr_chips = 1;
0260     rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
0261     rb532_nand_data.chip.partitions = rb532_partition_info;
0262     rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
0263 }
0264
0265
0266 static int __init plat_setup_devices(void)
0267 {
0268     /* Look for the CF card reader */
0269     if (!readl(IDT434_REG_BASE + DEV1MASK))
0270         rb532_devs[2] = NULL;   /* disable cf_slot0 at index 2 */
0271     else {
0272         cf_slot0_res[0].start =
0273             readl(IDT434_REG_BASE + DEV1BASE);
0274         cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
0275     }
0276
0277     /* Read the NAND resources from the device controller */
0278     nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
0279     nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
0280
0281     /* Read and map device controller 3 */
0282     dev3.base = ioremap(readl(IDT434_REG_BASE + DEV3BASE), 1);
0283
0284     if (!dev3.base) {
0285         printk(KERN_ERR "rb532: cannot remap device controller 3\n");
0286         return -ENXIO;
0287     }
0288
0289     /* Initialise the NAND device */
0290     rb532_nand_setup();
0291
0292     /* set the uart clock to the current cpu frequency */
0293     rb532_uart_res[0].uartclk = idt_cpu_freq;
0294
0295     gpiod_add_lookup_table(&cf_slot0_gpio_table);
0296     return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
0297 }
0298
0299 #ifdef CONFIG_NET
0300
0301 static int __init setup_kmac(char *s)
0302 {
0303     printk(KERN_INFO "korina mac = %s\n", s);
0304     if (!mac_pton(s, korina_dev0_data.mac))
0305         printk(KERN_ERR "Invalid mac\n");
0306     return 1;
0307 }
0308
0309 __setup("kmac=", setup_kmac);
0310
0311 #endif /* CONFIG_NET */
0312
0313 arch_initcall(plat_setup_devices);