mips/ralink/rt3883.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * Parts of this file are based on Ralink's 2.6.21 BSP
0005  *
0006  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0007  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0008  * Copyright (C) 2013 John Crispin <john@phrozen.org>
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013
0014 #include <asm/mipsregs.h>
0015 #include <asm/mach-ralink/ralink_regs.h>
0016 #include <asm/mach-ralink/rt3883.h>
0017
0018 #include "common.h"
0019
0020 void __init ralink_clk_init(void)
0021 {
0022     unsigned long cpu_rate, sys_rate;
0023     u32 syscfg0;
0024     u32 clksel;
0025     u32 ddr2;
0026
0027     syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
0028     clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
0029         RT3883_SYSCFG0_CPUCLK_MASK);
0030     ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
0031
0032     switch (clksel) {
0033     case RT3883_SYSCFG0_CPUCLK_250:
0034         cpu_rate = 250000000;
0035         sys_rate = (ddr2) ? 125000000 : 83000000;
0036         break;
0037     case RT3883_SYSCFG0_CPUCLK_384:
0038         cpu_rate = 384000000;
0039         sys_rate = (ddr2) ? 128000000 : 96000000;
0040         break;
0041     case RT3883_SYSCFG0_CPUCLK_480:
0042         cpu_rate = 480000000;
0043         sys_rate = (ddr2) ? 160000000 : 120000000;
0044         break;
0045     case RT3883_SYSCFG0_CPUCLK_500:
0046         cpu_rate = 500000000;
0047         sys_rate = (ddr2) ? 166000000 : 125000000;
0048         break;
0049     }
0050
0051     ralink_clk_add("cpu", cpu_rate);
0052     ralink_clk_add("10000100.timer", sys_rate);
0053     ralink_clk_add("10000120.watchdog", sys_rate);
0054     ralink_clk_add("10000500.uart", 40000000);
0055     ralink_clk_add("10000900.i2c", 40000000);
0056     ralink_clk_add("10000a00.i2s", 40000000);
0057     ralink_clk_add("10000b00.spi", sys_rate);
0058     ralink_clk_add("10000b40.spi", sys_rate);
0059     ralink_clk_add("10000c00.uartlite", 40000000);
0060     ralink_clk_add("10100000.ethernet", sys_rate);
0061     ralink_clk_add("10180000.wmac", 40000000);
0062 }
0063
0064 void __init ralink_of_remap(void)
0065 {
0066     rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
0067     rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
0068
0069     if (!rt_sysc_membase || !rt_memc_membase)
0070         panic("Failed to remap core resources");
0071 }
0072
0073 void __init prom_soc_init(struct ralink_soc_info *soc_info)
0074 {
0075     void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
0076     const char *name;
0077     u32 n0;
0078     u32 n1;
0079     u32 id;
0080
0081     n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
0082     n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
0083     id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
0084
0085     if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
0086         soc_info->compatible = "ralink,rt3883-soc";
0087         name = "RT3883";
0088     } else {
0089         panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
0090     }
0091
0092     snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
0093         "Ralink %s ver:%u eco:%u",
0094         name,
0095         (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
0096         (id & RT3883_REVID_ECO_ID_MASK));
0097
0098     soc_info->mem_base = RT3883_SDRAM_BASE;
0099     soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
0100     soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
0101
0102     ralink_soc = RT3883_SOC;
0103 }