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0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/bug.h>
0014
0015 #include <asm/io.h>
0016 #include <asm/mipsregs.h>
0017 #include <asm/mach-ralink/ralink_regs.h>
0018 #include <asm/mach-ralink/rt305x.h>
0019
0020 #include "common.h"
0021
0022 static unsigned long rt5350_get_mem_size(void)
0023 {
0024 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
0025 unsigned long ret;
0026 u32 t;
0027
0028 t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
0029 t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
0030 RT5350_SYSCFG0_DRAM_SIZE_MASK;
0031
0032 switch (t) {
0033 case RT5350_SYSCFG0_DRAM_SIZE_2M:
0034 ret = 2;
0035 break;
0036 case RT5350_SYSCFG0_DRAM_SIZE_8M:
0037 ret = 8;
0038 break;
0039 case RT5350_SYSCFG0_DRAM_SIZE_16M:
0040 ret = 16;
0041 break;
0042 case RT5350_SYSCFG0_DRAM_SIZE_32M:
0043 ret = 32;
0044 break;
0045 case RT5350_SYSCFG0_DRAM_SIZE_64M:
0046 ret = 64;
0047 break;
0048 default:
0049 panic("rt5350: invalid DRAM size: %u", t);
0050 break;
0051 }
0052
0053 return ret;
0054 }
0055
0056 void __init ralink_clk_init(void)
0057 {
0058 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
0059 unsigned long wmac_rate = 40000000;
0060
0061 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
0062
0063 if (soc_is_rt305x() || soc_is_rt3350()) {
0064 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
0065 RT305X_SYSCFG_CPUCLK_MASK;
0066 switch (t) {
0067 case RT305X_SYSCFG_CPUCLK_LOW:
0068 cpu_rate = 320000000;
0069 break;
0070 case RT305X_SYSCFG_CPUCLK_HIGH:
0071 cpu_rate = 384000000;
0072 break;
0073 }
0074 sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
0075 } else if (soc_is_rt3352()) {
0076 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
0077 RT3352_SYSCFG0_CPUCLK_MASK;
0078 switch (t) {
0079 case RT3352_SYSCFG0_CPUCLK_LOW:
0080 cpu_rate = 384000000;
0081 break;
0082 case RT3352_SYSCFG0_CPUCLK_HIGH:
0083 cpu_rate = 400000000;
0084 break;
0085 }
0086 sys_rate = wdt_rate = cpu_rate / 3;
0087 uart_rate = 40000000;
0088 } else if (soc_is_rt5350()) {
0089 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
0090 RT5350_SYSCFG0_CPUCLK_MASK;
0091 switch (t) {
0092 case RT5350_SYSCFG0_CPUCLK_360:
0093 cpu_rate = 360000000;
0094 sys_rate = cpu_rate / 3;
0095 break;
0096 case RT5350_SYSCFG0_CPUCLK_320:
0097 cpu_rate = 320000000;
0098 sys_rate = cpu_rate / 4;
0099 break;
0100 case RT5350_SYSCFG0_CPUCLK_300:
0101 cpu_rate = 300000000;
0102 sys_rate = cpu_rate / 3;
0103 break;
0104 default:
0105 BUG();
0106 }
0107 uart_rate = 40000000;
0108 wdt_rate = sys_rate;
0109 } else {
0110 BUG();
0111 }
0112
0113 if (soc_is_rt3352() || soc_is_rt5350()) {
0114 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
0115
0116 if (!(val & RT3352_CLKCFG0_XTAL_SEL))
0117 wmac_rate = 20000000;
0118 }
0119
0120 ralink_clk_add("cpu", cpu_rate);
0121 ralink_clk_add("sys", sys_rate);
0122 ralink_clk_add("10000900.i2c", uart_rate);
0123 ralink_clk_add("10000a00.i2s", uart_rate);
0124 ralink_clk_add("10000b00.spi", sys_rate);
0125 ralink_clk_add("10000b40.spi", sys_rate);
0126 ralink_clk_add("10000100.timer", wdt_rate);
0127 ralink_clk_add("10000120.watchdog", wdt_rate);
0128 ralink_clk_add("10000500.uart", uart_rate);
0129 ralink_clk_add("10000c00.uartlite", uart_rate);
0130 ralink_clk_add("10100000.ethernet", sys_rate);
0131 ralink_clk_add("10180000.wmac", wmac_rate);
0132 }
0133
0134 void __init ralink_of_remap(void)
0135 {
0136 rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
0137 rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
0138
0139 if (!rt_sysc_membase || !rt_memc_membase)
0140 panic("Failed to remap core resources");
0141 }
0142
0143 void __init prom_soc_init(struct ralink_soc_info *soc_info)
0144 {
0145 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
0146 unsigned char *name;
0147 u32 n0;
0148 u32 n1;
0149 u32 id;
0150
0151 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
0152 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
0153
0154 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
0155 unsigned long icache_sets;
0156
0157 icache_sets = (read_c0_config1() >> 22) & 7;
0158 if (icache_sets == 1) {
0159 ralink_soc = RT305X_SOC_RT3050;
0160 name = "RT3050";
0161 soc_info->compatible = "ralink,rt3050-soc";
0162 } else {
0163 ralink_soc = RT305X_SOC_RT3052;
0164 name = "RT3052";
0165 soc_info->compatible = "ralink,rt3052-soc";
0166 }
0167 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
0168 ralink_soc = RT305X_SOC_RT3350;
0169 name = "RT3350";
0170 soc_info->compatible = "ralink,rt3350-soc";
0171 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
0172 ralink_soc = RT305X_SOC_RT3352;
0173 name = "RT3352";
0174 soc_info->compatible = "ralink,rt3352-soc";
0175 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
0176 ralink_soc = RT305X_SOC_RT5350;
0177 name = "RT5350";
0178 soc_info->compatible = "ralink,rt5350-soc";
0179 } else {
0180 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
0181 }
0182
0183 id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
0184
0185 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
0186 "Ralink %s id:%u rev:%u",
0187 name,
0188 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
0189 (id & CHIP_ID_REV_MASK));
0190
0191 soc_info->mem_base = RT305X_SDRAM_BASE;
0192 if (soc_is_rt5350()) {
0193 soc_info->mem_size = rt5350_get_mem_size();
0194 } else if (soc_is_rt305x() || soc_is_rt3350()) {
0195 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
0196 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
0197 } else if (soc_is_rt3352()) {
0198 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
0199 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
0200 }
0201 }
