mips/ralink/rt288x.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * Parts of this file are based on Ralink's 2.6.21 BSP
0005  *
0006  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0007  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0008  * Copyright (C) 2013 John Crispin <john@phrozen.org>
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013
0014 #include <asm/mipsregs.h>
0015 #include <asm/mach-ralink/ralink_regs.h>
0016 #include <asm/mach-ralink/rt288x.h>
0017
0018 #include "common.h"
0019
0020 void __init ralink_clk_init(void)
0021 {
0022     unsigned long cpu_rate, wmac_rate = 40000000;
0023     u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
0024     t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
0025
0026     switch (t) {
0027     case SYSTEM_CONFIG_CPUCLK_250:
0028         cpu_rate = 250000000;
0029         break;
0030     case SYSTEM_CONFIG_CPUCLK_266:
0031         cpu_rate = 266666667;
0032         break;
0033     case SYSTEM_CONFIG_CPUCLK_280:
0034         cpu_rate = 280000000;
0035         break;
0036     case SYSTEM_CONFIG_CPUCLK_300:
0037         cpu_rate = 300000000;
0038         break;
0039     }
0040
0041     ralink_clk_add("cpu", cpu_rate);
0042     ralink_clk_add("300100.timer", cpu_rate / 2);
0043     ralink_clk_add("300120.watchdog", cpu_rate / 2);
0044     ralink_clk_add("300500.uart", cpu_rate / 2);
0045     ralink_clk_add("300900.i2c", cpu_rate / 2);
0046     ralink_clk_add("300c00.uartlite", cpu_rate / 2);
0047     ralink_clk_add("400000.ethernet", cpu_rate / 2);
0048     ralink_clk_add("480000.wmac", wmac_rate);
0049 }
0050
0051 void __init ralink_of_remap(void)
0052 {
0053     rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
0054     rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
0055
0056     if (!rt_sysc_membase || !rt_memc_membase)
0057         panic("Failed to remap core resources");
0058 }
0059
0060 void __init prom_soc_init(struct ralink_soc_info *soc_info)
0061 {
0062     void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
0063     const char *name;
0064     u32 n0;
0065     u32 n1;
0066     u32 id;
0067
0068     n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
0069     n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
0070     id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
0071
0072     if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
0073         soc_info->compatible = "ralink,r2880-soc";
0074         name = "RT2880";
0075     } else {
0076         panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
0077     }
0078
0079     snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
0080         "Ralink %s id:%u rev:%u",
0081         name,
0082         (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
0083         (id & CHIP_ID_REV_MASK));
0084
0085     soc_info->mem_base = RT2880_SDRAM_BASE;
0086     soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
0087     soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
0088
0089     ralink_soc = RT2880_SOC;
0090 }