mips/ralink/mt7621.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
0005  * Copyright (C) 2015 John Crispin <john@phrozen.org>
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/init.h>
0010 #include <linux/slab.h>
0011 #include <linux/sys_soc.h>
0012 #include <linux/memblock.h>
0013 #include <linux/pci.h>
0014 #include <linux/bug.h>
0015
0016 #include <asm/bootinfo.h>
0017 #include <asm/mipsregs.h>
0018 #include <asm/smp-ops.h>
0019 #include <asm/mips-cps.h>
0020 #include <asm/mach-ralink/ralink_regs.h>
0021 #include <asm/mach-ralink/mt7621.h>
0022
0023 #include "common.h"
0024
0025 #define MT7621_MEM_TEST_PATTERN         0xaa5555aa
0026
0027 static u32 detect_magic __initdata;
0028
0029 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
0030 {
0031     struct resource_entry *entry;
0032     resource_size_t mask;
0033
0034     entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
0035     if (!entry) {
0036         pr_err("Cannot get memory resource\n");
0037         return -EINVAL;
0038     }
0039
0040     if (mips_cps_numiocu(0)) {
0041         /*
0042          * Hardware doesn't accept mask values with 1s after
0043          * 0s (e.g. 0xffef), so warn if that's happen
0044          */
0045         mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;
0046         WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);
0047
0048         write_gcr_reg1_base(entry->res->start);
0049         write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
0050         pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
0051             (unsigned long long)read_gcr_reg1_base(),
0052             (unsigned long long)read_gcr_reg1_mask());
0053     }
0054
0055     return 0;
0056 }
0057
0058 phys_addr_t mips_cpc_default_phys_base(void)
0059 {
0060     panic("Cannot detect cpc address");
0061 }
0062
0063 static bool __init mt7621_addr_wraparound_test(phys_addr_t size)
0064 {
0065     void *dm = (void *)KSEG1ADDR(&detect_magic);
0066
0067     if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)
0068         return true;
0069     __raw_writel(MT7621_MEM_TEST_PATTERN, dm);
0070     if (__raw_readl(dm) != __raw_readl(dm + size))
0071         return false;
0072     __raw_writel(~MT7621_MEM_TEST_PATTERN, dm);
0073     return __raw_readl(dm) == __raw_readl(dm + size);
0074 }
0075
0076 static void __init mt7621_memory_detect(void)
0077 {
0078     phys_addr_t size;
0079
0080     for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) {
0081         if (mt7621_addr_wraparound_test(size)) {
0082             memblock_add(MT7621_LOWMEM_BASE, size);
0083             return;
0084         }
0085     }
0086
0087     memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
0088     memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
0089 }
0090
0091 void __init ralink_of_remap(void)
0092 {
0093     rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
0094     rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
0095
0096     if (!rt_sysc_membase || !rt_memc_membase)
0097         panic("Failed to remap core resources");
0098 }
0099
0100 static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
0101 {
0102     struct soc_device *soc_dev;
0103     struct soc_device_attribute *soc_dev_attr;
0104
0105     soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
0106     if (!soc_dev_attr)
0107         return;
0108
0109     soc_dev_attr->soc_id = "mt7621";
0110     soc_dev_attr->family = "Ralink";
0111
0112     if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
0113         (rev & CHIP_REV_ECO_MASK) == 1)
0114         soc_dev_attr->revision = "E2";
0115     else
0116         soc_dev_attr->revision = "E1";
0117
0118     soc_dev_attr->data = soc_info;
0119
0120     soc_dev = soc_device_register(soc_dev_attr);
0121     if (IS_ERR(soc_dev)) {
0122         kfree(soc_dev_attr);
0123         return;
0124     }
0125 }
0126
0127 void __init prom_soc_init(struct ralink_soc_info *soc_info)
0128 {
0129     void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
0130     unsigned char *name = NULL;
0131     u32 n0;
0132     u32 n1;
0133     u32 rev;
0134
0135     /* Early detection of CMP support */
0136     mips_cm_probe();
0137     mips_cpc_probe();
0138
0139     if (mips_cps_numiocu(0)) {
0140         /*
0141          * mips_cm_probe() wipes out bootloader
0142          * config for CM regions and we have to configure them
0143          * again. This SoC cannot talk to pamlbus devices
0144          * witout proper iocu region set up.
0145          *
0146          * FIXME: it would be better to do this with values
0147          * from DT, but we need this very early because
0148          * without this we cannot talk to pretty much anything
0149          * including serial.
0150          */
0151         write_gcr_reg0_base(MT7621_PALMBUS_BASE);
0152         write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
0153                     CM_GCR_REGn_MASK_CMTGT_IOCU0);
0154         __sync();
0155     }
0156
0157     n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
0158     n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
0159
0160     if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
0161         name = "MT7621";
0162         soc_info->compatible = "mediatek,mt7621-soc";
0163     } else {
0164         panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
0165     }
0166     ralink_soc = MT762X_SOC_MT7621AT;
0167     rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
0168
0169     snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
0170         "MediaTek %s ver:%u eco:%u",
0171         name,
0172         (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
0173         (rev & CHIP_REV_ECO_MASK));
0174
0175     soc_info->mem_detect = mt7621_memory_detect;
0176
0177     soc_dev_init(soc_info, rev);
0178
0179     if (!register_cps_smp_ops())
0180         return;
0181     if (!register_cmp_smp_ops())
0182         return;
0183     if (!register_vsmp_smp_ops())
0184         return;
0185 }