mips/ralink/irq.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
0005  * Copyright (C) 2013 John Crispin <john@phrozen.org>
0006  */
0007
0008 #include <linux/io.h>
0009 #include <linux/bitops.h>
0010 #include <linux/of_platform.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_irq.h>
0013 #include <linux/irqdomain.h>
0014 #include <linux/interrupt.h>
0015
0016 #include <asm/irq_cpu.h>
0017 #include <asm/mipsregs.h>
0018
0019 #include "common.h"
0020
0021 #define INTC_INT_GLOBAL     BIT(31)
0022
0023 #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
0024 #define RALINK_CPU_IRQ_PCI  (MIPS_CPU_IRQ_BASE + 4)
0025 #define RALINK_CPU_IRQ_FE   (MIPS_CPU_IRQ_BASE + 5)
0026 #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
0027 #define RALINK_CPU_IRQ_COUNTER  (MIPS_CPU_IRQ_BASE + 7)
0028
0029 /* we have a cascade of 8 irqs */
0030 #define RALINK_INTC_IRQ_BASE    8
0031
0032 /* we have 32 SoC irqs */
0033 #define RALINK_INTC_IRQ_COUNT   32
0034
0035 #define RALINK_INTC_IRQ_PERFC   (RALINK_INTC_IRQ_BASE + 9)
0036
0037 enum rt_intc_regs_enum {
0038     INTC_REG_STATUS0 = 0,
0039     INTC_REG_STATUS1,
0040     INTC_REG_TYPE,
0041     INTC_REG_RAW_STATUS,
0042     INTC_REG_ENABLE,
0043     INTC_REG_DISABLE,
0044 };
0045
0046 static u32 rt_intc_regs[] = {
0047     [INTC_REG_STATUS0] = 0x00,
0048     [INTC_REG_STATUS1] = 0x04,
0049     [INTC_REG_TYPE] = 0x20,
0050     [INTC_REG_RAW_STATUS] = 0x30,
0051     [INTC_REG_ENABLE] = 0x34,
0052     [INTC_REG_DISABLE] = 0x38,
0053 };
0054
0055 static void __iomem *rt_intc_membase;
0056
0057 static int rt_perfcount_irq;
0058
0059 static inline void rt_intc_w32(u32 val, unsigned reg)
0060 {
0061     __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
0062 }
0063
0064 static inline u32 rt_intc_r32(unsigned reg)
0065 {
0066     return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
0067 }
0068
0069 static void ralink_intc_irq_unmask(struct irq_data *d)
0070 {
0071     rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
0072 }
0073
0074 static void ralink_intc_irq_mask(struct irq_data *d)
0075 {
0076     rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
0077 }
0078
0079 static struct irq_chip ralink_intc_irq_chip = {
0080     .name       = "INTC",
0081     .irq_unmask = ralink_intc_irq_unmask,
0082     .irq_mask   = ralink_intc_irq_mask,
0083     .irq_mask_ack   = ralink_intc_irq_mask,
0084 };
0085
0086 int get_c0_perfcount_int(void)
0087 {
0088     return rt_perfcount_irq;
0089 }
0090 EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
0091
0092 unsigned int get_c0_compare_int(void)
0093 {
0094     return CP0_LEGACY_COMPARE_IRQ;
0095 }
0096
0097 static void ralink_intc_irq_handler(struct irq_desc *desc)
0098 {
0099     u32 pending = rt_intc_r32(INTC_REG_STATUS0);
0100
0101     if (pending) {
0102         struct irq_domain *domain = irq_desc_get_handler_data(desc);
0103         generic_handle_domain_irq(domain, __ffs(pending));
0104     } else {
0105         spurious_interrupt();
0106     }
0107 }
0108
0109 asmlinkage void plat_irq_dispatch(void)
0110 {
0111     unsigned long pending;
0112
0113     pending = read_c0_status() & read_c0_cause() & ST0_IM;
0114
0115     if (pending & STATUSF_IP7)
0116         do_IRQ(RALINK_CPU_IRQ_COUNTER);
0117
0118     else if (pending & STATUSF_IP5)
0119         do_IRQ(RALINK_CPU_IRQ_FE);
0120
0121     else if (pending & STATUSF_IP6)
0122         do_IRQ(RALINK_CPU_IRQ_WIFI);
0123
0124     else if (pending & STATUSF_IP4)
0125         do_IRQ(RALINK_CPU_IRQ_PCI);
0126
0127     else if (pending & STATUSF_IP2)
0128         do_IRQ(RALINK_CPU_IRQ_INTC);
0129
0130     else
0131         spurious_interrupt();
0132 }
0133
0134 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
0135 {
0136     irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
0137
0138     return 0;
0139 }
0140
0141 static const struct irq_domain_ops irq_domain_ops = {
0142     .xlate = irq_domain_xlate_onecell,
0143     .map = intc_map,
0144 };
0145
0146 static int __init intc_of_init(struct device_node *node,
0147                    struct device_node *parent)
0148 {
0149     struct resource res;
0150     struct irq_domain *domain;
0151     int irq;
0152
0153     if (!of_property_read_u32_array(node, "ralink,intc-registers",
0154                     rt_intc_regs, 6))
0155         pr_info("intc: using register map from devicetree\n");
0156
0157     irq = irq_of_parse_and_map(node, 0);
0158     if (!irq)
0159         panic("Failed to get INTC IRQ");
0160
0161     if (of_address_to_resource(node, 0, &res))
0162         panic("Failed to get intc memory range");
0163
0164     if (!request_mem_region(res.start, resource_size(&res),
0165                 res.name))
0166         pr_err("Failed to request intc memory");
0167
0168     rt_intc_membase = ioremap(res.start,
0169                     resource_size(&res));
0170     if (!rt_intc_membase)
0171         panic("Failed to remap intc memory");
0172
0173     /* disable all interrupts */
0174     rt_intc_w32(~0, INTC_REG_DISABLE);
0175
0176     /* route all INTC interrupts to MIPS HW0 interrupt */
0177     rt_intc_w32(0, INTC_REG_TYPE);
0178
0179     domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
0180             RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
0181     if (!domain)
0182         panic("Failed to add irqdomain");
0183
0184     rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
0185
0186     irq_set_chained_handler_and_data(irq, ralink_intc_irq_handler, domain);
0187
0188     /* tell the kernel which irq is used for performance monitoring */
0189     rt_perfcount_irq = irq_create_mapping(domain, 9);
0190
0191     return 0;
0192 }
0193
0194 static struct of_device_id __initdata of_irq_ids[] = {
0195     { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
0196     { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
0197     {},
0198 };
0199
0200 void __init arch_init_irq(void)
0201 {
0202     of_irq_init(of_irq_ids);
0203 }
0204