mips/pci/pci.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *
0004  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
0005  * Copyright (C) 2011 Wind River Systems,
0006  *   written by Ralf Baechle (ralf@linux-mips.org)
0007  */
0008 #include <linux/bug.h>
0009 #include <linux/kernel.h>
0010 #include <linux/mm.h>
0011 #include <linux/memblock.h>
0012 #include <linux/export.h>
0013 #include <linux/init.h>
0014 #include <linux/types.h>
0015 #include <linux/pci.h>
0016 #include <linux/of_address.h>
0017
0018 #include <asm/cpu-info.h>
0019
0020 unsigned long PCIBIOS_MIN_IO;
0021 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
0022
0023 unsigned long PCIBIOS_MIN_MEM;
0024 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
0025
0026 static int __init pcibios_set_cache_line_size(void)
0027 {
0028     unsigned int lsize;
0029
0030     /*
0031      * Set PCI cacheline size to that of the highest level in the
0032      * cache hierarchy.
0033      */
0034     lsize = cpu_dcache_line_size();
0035     lsize = cpu_scache_line_size() ? : lsize;
0036     lsize = cpu_tcache_line_size() ? : lsize;
0037
0038     BUG_ON(!lsize);
0039
0040     pci_dfl_cache_line_size = lsize >> 2;
0041
0042     pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
0043     return 0;
0044 }
0045 arch_initcall(pcibios_set_cache_line_size);
0046
0047 void pci_resource_to_user(const struct pci_dev *dev, int bar,
0048               const struct resource *rsrc, resource_size_t *start,
0049               resource_size_t *end)
0050 {
0051     phys_addr_t size = resource_size(rsrc);
0052
0053     *start = fixup_bigphys_addr(rsrc->start, size);
0054     *end = rsrc->start + size - 1;
0055 }