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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
0004  * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
0005  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
0006  */
0007 #include <linux/kernel.h>
0008 #include <linux/export.h>
0009 #include <linux/pci.h>
0010 #include <linux/smp.h>
0011 #include <linux/dma-direct.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/platform_data/xtalk-bridge.h>
0014 #include <linux/nvmem-consumer.h>
0015 #include <linux/crc16.h>
0016 #include <linux/irqdomain.h>
0017 
0018 #include <asm/pci/bridge.h>
0019 #include <asm/paccess.h>
0020 #include <asm/sn/irq_alloc.h>
0021 #include <asm/sn/ioc3.h>
0022 
0023 #define CRC16_INIT  0
0024 #define CRC16_VALID 0xb001
0025 
0026 /*
0027  * Common phys<->dma mapping for platforms using pci xtalk bridge
0028  */
0029 dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
0030 {
0031     struct pci_dev *pdev = to_pci_dev(dev);
0032     struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
0033 
0034     return bc->baddr + paddr;
0035 }
0036 
0037 phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
0038 {
0039     return dma_addr & ~(0xffUL << 56);
0040 }
0041 
0042 /*
0043  * Most of the IOC3 PCI config register aren't present
0044  * we emulate what is needed for a normal PCI enumeration
0045  */
0046 static int ioc3_cfg_rd(void *addr, int where, int size, u32 *value, u32 sid)
0047 {
0048     u32 cf, shift, mask;
0049 
0050     switch (where & ~3) {
0051     case 0x00 ... 0x10:
0052     case 0x40 ... 0x44:
0053         if (get_dbe(cf, (u32 *)addr))
0054             return PCIBIOS_DEVICE_NOT_FOUND;
0055         break;
0056     case 0x2c:
0057         cf = sid;
0058         break;
0059     case 0x3c:
0060         /* emulate sane interrupt pin value */
0061         cf = 0x00000100;
0062         break;
0063     default:
0064         cf = 0;
0065         break;
0066     }
0067     shift = (where & 3) << 3;
0068     mask = 0xffffffffU >> ((4 - size) << 3);
0069     *value = (cf >> shift) & mask;
0070 
0071     return PCIBIOS_SUCCESSFUL;
0072 }
0073 
0074 static int ioc3_cfg_wr(void *addr, int where, int size, u32 value)
0075 {
0076     u32 cf, shift, mask, smask;
0077 
0078     if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
0079         return PCIBIOS_SUCCESSFUL;
0080 
0081     if (get_dbe(cf, (u32 *)addr))
0082         return PCIBIOS_DEVICE_NOT_FOUND;
0083 
0084     shift = ((where & 3) << 3);
0085     mask = (0xffffffffU >> ((4 - size) << 3));
0086     smask = mask << shift;
0087 
0088     cf = (cf & ~smask) | ((value & mask) << shift);
0089     if (put_dbe(cf, (u32 *)addr))
0090         return PCIBIOS_DEVICE_NOT_FOUND;
0091 
0092     return PCIBIOS_SUCCESSFUL;
0093 }
0094 
0095 static void bridge_disable_swapping(struct pci_dev *dev)
0096 {
0097     struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
0098     int slot = PCI_SLOT(dev->devfn);
0099 
0100     /* Turn off byte swapping */
0101     bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
0102     bridge_read(bc, b_widget.w_tflush); /* Flush */
0103 }
0104 
0105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
0106     bridge_disable_swapping);
0107 
0108 
0109 /*
0110  * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is
0111  * not really documented, so right now I can't write code which uses it.
0112  * Therefore we use type 0 accesses for now even though they won't work
0113  * correctly for PCI-to-PCI bridges.
0114  *
0115  * The function is complicated by the ultimate brokenness of the IOC3 chip
0116  * which is used in SGI systems.  The IOC3 can only handle 32-bit PCI
0117  * accesses and does only decode parts of it's address space.
0118  */
0119 static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
0120                  int where, int size, u32 *value)
0121 {
0122     struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
0123     struct bridge_regs *bridge = bc->base;
0124     int slot = PCI_SLOT(devfn);
0125     int fn = PCI_FUNC(devfn);
0126     void *addr;
0127     u32 cf;
0128     int res;
0129 
0130     addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
0131     if (get_dbe(cf, (u32 *)addr))
0132         return PCIBIOS_DEVICE_NOT_FOUND;
0133 
0134     /*
0135      * IOC3 is broken beyond belief ...  Don't even give the
0136      * generic PCI code a chance to look at it for real ...
0137      */
0138     if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
0139         addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
0140         return ioc3_cfg_rd(addr, where, size, value,
0141                    bc->ioc3_sid[slot]);
0142     }
0143 
0144     addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
0145 
0146     if (size == 1)
0147         res = get_dbe(*value, (u8 *)addr);
0148     else if (size == 2)
0149         res = get_dbe(*value, (u16 *)addr);
0150     else
0151         res = get_dbe(*value, (u32 *)addr);
0152 
0153     return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
0154 }
0155 
0156 static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
0157                  int where, int size, u32 *value)
0158 {
0159     struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
0160     struct bridge_regs *bridge = bc->base;
0161     int busno = bus->number;
0162     int slot = PCI_SLOT(devfn);
0163     int fn = PCI_FUNC(devfn);
0164     void *addr;
0165     u32 cf;
0166     int res;
0167 
0168     bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
0169     addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
0170     if (get_dbe(cf, (u32 *)addr))
0171         return PCIBIOS_DEVICE_NOT_FOUND;
0172 
0173     /*
0174      * IOC3 is broken beyond belief ...  Don't even give the
0175      * generic PCI code a chance to look at it for real ...
0176      */
0177     if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
0178         addr = &bridge->b_type1_cfg.c[(fn << 8) | (where & ~3)];
0179         return ioc3_cfg_rd(addr, where, size, value,
0180                    bc->ioc3_sid[slot]);
0181     }
0182 
0183     addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
0184 
0185     if (size == 1)
0186         res = get_dbe(*value, (u8 *)addr);
0187     else if (size == 2)
0188         res = get_dbe(*value, (u16 *)addr);
0189     else
0190         res = get_dbe(*value, (u32 *)addr);
0191 
0192     return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
0193 }
0194 
0195 static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
0196                int where, int size, u32 *value)
0197 {
0198     if (!pci_is_root_bus(bus))
0199         return pci_conf1_read_config(bus, devfn, where, size, value);
0200 
0201     return pci_conf0_read_config(bus, devfn, where, size, value);
0202 }
0203 
0204 static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
0205                   int where, int size, u32 value)
0206 {
0207     struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
0208     struct bridge_regs *bridge = bc->base;
0209     int slot = PCI_SLOT(devfn);
0210     int fn = PCI_FUNC(devfn);
0211     void *addr;
0212     u32 cf;
0213     int res;
0214 
0215     addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
0216     if (get_dbe(cf, (u32 *)addr))
0217         return PCIBIOS_DEVICE_NOT_FOUND;
0218 
0219     /*
0220      * IOC3 is broken beyond belief ...  Don't even give the
0221      * generic PCI code a chance to look at it for real ...
0222      */
0223     if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
0224         addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
0225         return ioc3_cfg_wr(addr, where, size, value);
0226     }
0227 
0228     addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
0229 
0230     if (size == 1)
0231         res = put_dbe(value, (u8 *)addr);
0232     else if (size == 2)
0233         res = put_dbe(value, (u16 *)addr);
0234     else
0235         res = put_dbe(value, (u32 *)addr);
0236 
0237     if (res)
0238         return PCIBIOS_DEVICE_NOT_FOUND;
0239 
0240     return PCIBIOS_SUCCESSFUL;
0241 }
0242 
0243 static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
0244                   int where, int size, u32 value)
0245 {
0246     struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
0247     struct bridge_regs *bridge = bc->base;
0248     int slot = PCI_SLOT(devfn);
0249     int fn = PCI_FUNC(devfn);
0250     int busno = bus->number;
0251     void *addr;
0252     u32 cf;
0253     int res;
0254 
0255     bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
0256     addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
0257     if (get_dbe(cf, (u32 *)addr))
0258         return PCIBIOS_DEVICE_NOT_FOUND;
0259 
0260     /*
0261      * IOC3 is broken beyond belief ...  Don't even give the
0262      * generic PCI code a chance to look at it for real ...
0263      */
0264     if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
0265         addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
0266         return ioc3_cfg_wr(addr, where, size, value);
0267     }
0268 
0269     addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
0270 
0271     if (size == 1)
0272         res = put_dbe(value, (u8 *)addr);
0273     else if (size == 2)
0274         res = put_dbe(value, (u16 *)addr);
0275     else
0276         res = put_dbe(value, (u32 *)addr);
0277 
0278     if (res)
0279         return PCIBIOS_DEVICE_NOT_FOUND;
0280 
0281     return PCIBIOS_SUCCESSFUL;
0282 }
0283 
0284 static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
0285     int where, int size, u32 value)
0286 {
0287     if (!pci_is_root_bus(bus))
0288         return pci_conf1_write_config(bus, devfn, where, size, value);
0289 
0290     return pci_conf0_write_config(bus, devfn, where, size, value);
0291 }
0292 
0293 static struct pci_ops bridge_pci_ops = {
0294     .read    = pci_read_config,
0295     .write   = pci_write_config,
0296 };
0297 
0298 struct bridge_irq_chip_data {
0299     struct bridge_controller *bc;
0300     nasid_t nasid;
0301 };
0302 
0303 static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
0304                    bool force)
0305 {
0306 #ifdef CONFIG_NUMA
0307     struct bridge_irq_chip_data *data = d->chip_data;
0308     int bit = d->parent_data->hwirq;
0309     int pin = d->hwirq;
0310     int ret, cpu;
0311 
0312     ret = irq_chip_set_affinity_parent(d, mask, force);
0313     if (ret >= 0) {
0314         cpu = cpumask_first_and(mask, cpu_online_mask);
0315         data->nasid = cpu_to_node(cpu);
0316         bridge_write(data->bc, b_int_addr[pin].addr,
0317                  (((data->bc->intr_addr >> 30) & 0x30000) |
0318                   bit | (data->nasid << 8)));
0319         bridge_read(data->bc, b_wid_tflush);
0320     }
0321     return ret;
0322 #else
0323     return irq_chip_set_affinity_parent(d, mask, force);
0324 #endif
0325 }
0326 
0327 struct irq_chip bridge_irq_chip = {
0328     .name             = "BRIDGE",
0329     .irq_mask         = irq_chip_mask_parent,
0330     .irq_unmask       = irq_chip_unmask_parent,
0331     .irq_set_affinity = bridge_set_affinity
0332 };
0333 
0334 static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq,
0335                    unsigned int nr_irqs, void *arg)
0336 {
0337     struct bridge_irq_chip_data *data;
0338     struct irq_alloc_info *info = arg;
0339     int ret;
0340 
0341     if (nr_irqs > 1 || !info)
0342         return -EINVAL;
0343 
0344     data = kzalloc(sizeof(*data), GFP_KERNEL);
0345     if (!data)
0346         return -ENOMEM;
0347 
0348     ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
0349     if (ret >= 0) {
0350         data->bc = info->ctrl;
0351         data->nasid = info->nasid;
0352         irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip,
0353                     data, handle_level_irq, NULL, NULL);
0354     } else {
0355         kfree(data);
0356     }
0357 
0358     return ret;
0359 }
0360 
0361 static void bridge_domain_free(struct irq_domain *domain, unsigned int virq,
0362                    unsigned int nr_irqs)
0363 {
0364     struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
0365 
0366     if (nr_irqs)
0367         return;
0368 
0369     kfree(irqd->chip_data);
0370     irq_domain_free_irqs_top(domain, virq, nr_irqs);
0371 }
0372 
0373 static int bridge_domain_activate(struct irq_domain *domain,
0374                   struct irq_data *irqd, bool reserve)
0375 {
0376     struct bridge_irq_chip_data *data = irqd->chip_data;
0377     struct bridge_controller *bc = data->bc;
0378     int bit = irqd->parent_data->hwirq;
0379     int pin = irqd->hwirq;
0380     u32 device;
0381 
0382     bridge_write(bc, b_int_addr[pin].addr,
0383              (((bc->intr_addr >> 30) & 0x30000) |
0384               bit | (data->nasid << 8)));
0385     bridge_set(bc, b_int_enable, (1 << pin));
0386     bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
0387 
0388     /*
0389      * Enable sending of an interrupt clear packet to the hub on a high to
0390      * low transition of the interrupt pin.
0391      *
0392      * IRIX sets additional bits in the address which are documented as
0393      * reserved in the bridge docs.
0394      */
0395     bridge_set(bc, b_int_mode, (1UL << pin));
0396 
0397     /*
0398      * We assume the bridge to have a 1:1 mapping between devices
0399      * (slots) and intr pins.
0400      */
0401     device = bridge_read(bc, b_int_device);
0402     device &= ~(7 << (pin*3));
0403     device |= (pin << (pin*3));
0404     bridge_write(bc, b_int_device, device);
0405 
0406     bridge_read(bc, b_wid_tflush);
0407     return 0;
0408 }
0409 
0410 static void bridge_domain_deactivate(struct irq_domain *domain,
0411                      struct irq_data *irqd)
0412 {
0413     struct bridge_irq_chip_data *data = irqd->chip_data;
0414 
0415     bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
0416     bridge_read(data->bc, b_wid_tflush);
0417 }
0418 
0419 static const struct irq_domain_ops bridge_domain_ops = {
0420     .alloc      = bridge_domain_alloc,
0421     .free       = bridge_domain_free,
0422     .activate   = bridge_domain_activate,
0423     .deactivate = bridge_domain_deactivate
0424 };
0425 
0426 /*
0427  * All observed requests have pin == 1. We could have a global here, that
0428  * gets incremented and returned every time - unfortunately, pci_map_irq
0429  * may be called on the same device over and over, and need to return the
0430  * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
0431  *
0432  * A given PCI device, in general, should be able to intr any of the cpus
0433  * on any one of the hubs connected to its xbow.
0434  */
0435 static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0436 {
0437     struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
0438     struct irq_alloc_info info;
0439     int irq;
0440 
0441     switch (pin) {
0442     case PCI_INTERRUPT_UNKNOWN:
0443     case PCI_INTERRUPT_INTA:
0444     case PCI_INTERRUPT_INTC:
0445         pin = 0;
0446         break;
0447     case PCI_INTERRUPT_INTB:
0448     case PCI_INTERRUPT_INTD:
0449         pin = 1;
0450     }
0451 
0452     irq = bc->pci_int[slot][pin];
0453     if (irq == -1) {
0454         info.ctrl = bc;
0455         info.nasid = bc->nasid;
0456         info.pin = bc->int_mapping[slot][pin];
0457 
0458         irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
0459         if (irq < 0)
0460             return irq;
0461 
0462         bc->pci_int[slot][pin] = irq;
0463     }
0464     return irq;
0465 }
0466 
0467 #define IOC3_SID(sid)   (PCI_VENDOR_ID_SGI | ((sid) << 16))
0468 
0469 static void bridge_setup_ip27_baseio6g(struct bridge_controller *bc)
0470 {
0471     bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO6G);
0472     bc->ioc3_sid[6] = IOC3_SID(IOC3_SUBSYS_IP27_MIO);
0473     bc->int_mapping[2][1] = 4;
0474     bc->int_mapping[6][1] = 6;
0475 }
0476 
0477 static void bridge_setup_ip27_baseio(struct bridge_controller *bc)
0478 {
0479     bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO);
0480     bc->int_mapping[2][1] = 4;
0481 }
0482 
0483 static void bridge_setup_ip29_baseio(struct bridge_controller *bc)
0484 {
0485     bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP29_SYSBOARD);
0486     bc->int_mapping[2][1] = 3;
0487 }
0488 
0489 static void bridge_setup_ip30_sysboard(struct bridge_controller *bc)
0490 {
0491     bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP30_SYSBOARD);
0492     bc->int_mapping[2][1] = 4;
0493 }
0494 
0495 static void bridge_setup_menet(struct bridge_controller *bc)
0496 {
0497     bc->ioc3_sid[0] = IOC3_SID(IOC3_SUBSYS_MENET);
0498     bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_MENET);
0499     bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_MENET);
0500     bc->ioc3_sid[3] = IOC3_SID(IOC3_SUBSYS_MENET4);
0501 }
0502 
0503 static void bridge_setup_io7(struct bridge_controller *bc)
0504 {
0505     bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO7);
0506 }
0507 
0508 static void bridge_setup_io8(struct bridge_controller *bc)
0509 {
0510     bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO8);
0511 }
0512 
0513 static void bridge_setup_io9(struct bridge_controller *bc)
0514 {
0515     bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_IO9);
0516 }
0517 
0518 static void bridge_setup_ip34_fuel_sysboard(struct bridge_controller *bc)
0519 {
0520     bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IP34_SYSBOARD);
0521 }
0522 
0523 #define BRIDGE_BOARD_SETUP(_partno, _setup) \
0524     { .match = _partno, .setup = _setup }
0525 
0526 static const struct {
0527     char *match;
0528     void (*setup)(struct bridge_controller *bc);
0529 } bridge_ioc3_devid[] = {
0530     BRIDGE_BOARD_SETUP("030-0734-", bridge_setup_ip27_baseio6g),
0531     BRIDGE_BOARD_SETUP("030-0880-", bridge_setup_ip27_baseio6g),
0532     BRIDGE_BOARD_SETUP("030-1023-", bridge_setup_ip27_baseio),
0533     BRIDGE_BOARD_SETUP("030-1124-", bridge_setup_ip27_baseio),
0534     BRIDGE_BOARD_SETUP("030-1025-", bridge_setup_ip29_baseio),
0535     BRIDGE_BOARD_SETUP("030-1244-", bridge_setup_ip29_baseio),
0536     BRIDGE_BOARD_SETUP("030-1389-", bridge_setup_ip29_baseio),
0537     BRIDGE_BOARD_SETUP("030-0887-", bridge_setup_ip30_sysboard),
0538     BRIDGE_BOARD_SETUP("030-1467-", bridge_setup_ip30_sysboard),
0539     BRIDGE_BOARD_SETUP("030-0873-", bridge_setup_menet),
0540     BRIDGE_BOARD_SETUP("030-1557-", bridge_setup_io7),
0541     BRIDGE_BOARD_SETUP("030-1673-", bridge_setup_io8),
0542     BRIDGE_BOARD_SETUP("030-1771-", bridge_setup_io9),
0543     BRIDGE_BOARD_SETUP("030-1707-", bridge_setup_ip34_fuel_sysboard),
0544 };
0545 
0546 static void bridge_setup_board(struct bridge_controller *bc, char *partnum)
0547 {
0548     int i;
0549 
0550     for (i = 0; i < ARRAY_SIZE(bridge_ioc3_devid); i++)
0551         if (!strncmp(partnum, bridge_ioc3_devid[i].match,
0552                  strlen(bridge_ioc3_devid[i].match))) {
0553             bridge_ioc3_devid[i].setup(bc);
0554         }
0555 }
0556 
0557 static int bridge_nvmem_match(struct device *dev, const void *data)
0558 {
0559     const char *name = dev_name(dev);
0560     const char *prefix = data;
0561 
0562     if (strlen(name) < strlen(prefix))
0563         return 0;
0564 
0565     return memcmp(prefix, dev_name(dev), strlen(prefix)) == 0;
0566 }
0567 
0568 static int bridge_get_partnum(u64 baddr, char *partnum)
0569 {
0570     struct nvmem_device *nvmem;
0571     char prefix[24];
0572     u8 prom[64];
0573     int i, j;
0574     int ret;
0575 
0576     snprintf(prefix, sizeof(prefix), "bridge-%012llx-0b-", baddr);
0577 
0578     nvmem = nvmem_device_find(prefix, bridge_nvmem_match);
0579     if (IS_ERR(nvmem))
0580         return PTR_ERR(nvmem);
0581 
0582     ret = nvmem_device_read(nvmem, 0, 64, prom);
0583     nvmem_device_put(nvmem);
0584 
0585     if (ret != 64)
0586         return ret;
0587 
0588     if (crc16(CRC16_INIT, prom, 32) != CRC16_VALID ||
0589         crc16(CRC16_INIT, prom + 32, 32) != CRC16_VALID)
0590         return -EINVAL;
0591 
0592     /* Assemble part number */
0593     j = 0;
0594     for (i = 0; i < 19; i++)
0595         if (prom[i + 11] != ' ')
0596             partnum[j++] = prom[i + 11];
0597 
0598     for (i = 0; i < 6; i++)
0599         if (prom[i + 32] != ' ')
0600             partnum[j++] = prom[i + 32];
0601 
0602     partnum[j] = 0;
0603 
0604     return 0;
0605 }
0606 
0607 static int bridge_probe(struct platform_device *pdev)
0608 {
0609     struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev);
0610     struct device *dev = &pdev->dev;
0611     struct bridge_controller *bc;
0612     struct pci_host_bridge *host;
0613     struct irq_domain *domain, *parent;
0614     struct fwnode_handle *fn;
0615     char partnum[26];
0616     int slot;
0617     int err;
0618 
0619     /* get part number from one wire prom */
0620     if (bridge_get_partnum(virt_to_phys((void *)bd->bridge_addr), partnum))
0621         return -EPROBE_DEFER; /* not available yet */
0622 
0623     parent = irq_get_default_host();
0624     if (!parent)
0625         return -ENODEV;
0626     fn = irq_domain_alloc_named_fwnode("BRIDGE");
0627     if (!fn)
0628         return -ENOMEM;
0629     domain = irq_domain_create_hierarchy(parent, 0, 8, fn,
0630                          &bridge_domain_ops, NULL);
0631     if (!domain) {
0632         irq_domain_free_fwnode(fn);
0633         return -ENOMEM;
0634     }
0635 
0636     pci_set_flags(PCI_PROBE_ONLY);
0637 
0638     host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
0639     if (!host) {
0640         err = -ENOMEM;
0641         goto err_remove_domain;
0642     }
0643 
0644     bc = pci_host_bridge_priv(host);
0645 
0646     bc->busn.name       = "Bridge PCI busn";
0647     bc->busn.start      = 0;
0648     bc->busn.end        = 0xff;
0649     bc->busn.flags      = IORESOURCE_BUS;
0650 
0651     bc->domain      = domain;
0652 
0653     pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset);
0654     pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset);
0655     pci_add_resource(&host->windows, &bc->busn);
0656 
0657     err = devm_request_pci_bus_resources(dev, &host->windows);
0658     if (err < 0)
0659         goto err_free_resource;
0660 
0661     bc->nasid = bd->nasid;
0662 
0663     bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
0664     bc->base = (struct bridge_regs *)bd->bridge_addr;
0665     bc->intr_addr = bd->intr_addr;
0666 
0667     /*
0668      * Clear all pending interrupts.
0669      */
0670     bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
0671 
0672     /*
0673      * Until otherwise set up, assume all interrupts are from slot 0
0674      */
0675     bridge_write(bc, b_int_device, 0x0);
0676 
0677     /*
0678      * disable swapping for big windows
0679      */
0680     bridge_clr(bc, b_wid_control,
0681            BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP);
0682 #ifdef CONFIG_PAGE_SIZE_4KB
0683     bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
0684 #else /* 16kB or larger */
0685     bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
0686 #endif
0687 
0688     /*
0689      * Hmm...  IRIX sets additional bits in the address which
0690      * are documented as reserved in the bridge docs.
0691      */
0692     bridge_write(bc, b_wid_int_upper,
0693              ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
0694     bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
0695     bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */
0696     bridge_write(bc, b_int_enable, 0);
0697 
0698     for (slot = 0; slot < 8; slot++) {
0699         bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
0700         bc->pci_int[slot][0] = -1;
0701         bc->pci_int[slot][1] = -1;
0702         /* default interrupt pin mapping */
0703         bc->int_mapping[slot][0] = slot;
0704         bc->int_mapping[slot][1] = slot ^ 4;
0705     }
0706     bridge_read(bc, b_wid_tflush);    /* wait until Bridge PIO complete */
0707 
0708     bridge_setup_board(bc, partnum);
0709 
0710     host->dev.parent = dev;
0711     host->sysdata = bc;
0712     host->busnr = 0;
0713     host->ops = &bridge_pci_ops;
0714     host->map_irq = bridge_map_irq;
0715     host->swizzle_irq = pci_common_swizzle;
0716 
0717     err = pci_scan_root_bus_bridge(host);
0718     if (err < 0)
0719         goto err_free_resource;
0720 
0721     pci_bus_claim_resources(host->bus);
0722     pci_bus_add_devices(host->bus);
0723 
0724     platform_set_drvdata(pdev, host->bus);
0725 
0726     return 0;
0727 
0728 err_free_resource:
0729     pci_free_resource_list(&host->windows);
0730 err_remove_domain:
0731     irq_domain_remove(domain);
0732     irq_domain_free_fwnode(fn);
0733     return err;
0734 }
0735 
0736 static int bridge_remove(struct platform_device *pdev)
0737 {
0738     struct pci_bus *bus = platform_get_drvdata(pdev);
0739     struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
0740     struct fwnode_handle *fn = bc->domain->fwnode;
0741 
0742     irq_domain_remove(bc->domain);
0743     irq_domain_free_fwnode(fn);
0744     pci_lock_rescan_remove();
0745     pci_stop_root_bus(bus);
0746     pci_remove_root_bus(bus);
0747     pci_unlock_rescan_remove();
0748 
0749     return 0;
0750 }
0751 
0752 static struct platform_driver bridge_driver = {
0753     .probe  = bridge_probe,
0754     .remove = bridge_remove,
0755     .driver = {
0756         .name = "xtalk-bridge",
0757     }
0758 };
0759 
0760 builtin_platform_driver(bridge_driver);
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