mips/pci/pci-sb1250.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2001,2002,2003 Broadcom Corporation
0004  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
0005  */
0006
0007 /*
0008  * BCM1250-specific PCI support
0009  *
0010  * This module provides the glue between Linux's PCI subsystem
0011  * and the hardware.  We basically provide glue for accessing
0012  * configuration space, and set up the translation for I/O
0013  * space accesses.
0014  *
0015  * To access configuration space, we use ioremap.  In the 32-bit
0016  * kernel, this consumes either 4 or 8 page table pages, and 16MB of
0017  * kernel mapped memory.  Hopefully neither of these should be a huge
0018  * problem.
0019  */
0020 #include <linux/types.h>
0021 #include <linux/pci.h>
0022 #include <linux/kernel.h>
0023 #include <linux/init.h>
0024 #include <linux/mm.h>
0025 #include <linux/console.h>
0026 #include <linux/tty.h>
0027 #include <linux/vt.h>
0028
0029 #include <asm/io.h>
0030
0031 #include <asm/sibyte/sb1250_defs.h>
0032 #include <asm/sibyte/sb1250_regs.h>
0033 #include <asm/sibyte/sb1250_scd.h>
0034 #include <asm/sibyte/board.h>
0035
0036 /*
0037  * Macros for calculating offsets into config space given a device
0038  * structure or dev/fun/reg
0039  */
0040 #define CFGOFFSET(bus, devfn, where) (((bus)<<16) + ((devfn)<<8) + (where))
0041 #define CFGADDR(bus, devfn, where)   CFGOFFSET((bus)->number, (devfn), where)
0042
0043 static void *cfg_space;
0044
0045 #define PCI_BUS_ENABLED 1
0046 #define LDT_BUS_ENABLED 2
0047 #define PCI_DEVICE_MODE 4
0048
0049 static int sb1250_bus_status;
0050
0051 #define PCI_BRIDGE_DEVICE  0
0052 #define LDT_BRIDGE_DEVICE  1
0053
0054 #ifdef CONFIG_SIBYTE_HAS_LDT
0055 /*
0056  * HT's level-sensitive interrupts require EOI, which is generated
0057  * through a 4MB memory-mapped region
0058  */
0059 unsigned long ldt_eoi_space;
0060 #endif
0061
0062 /*
0063  * Read/write 32-bit values in config space.
0064  */
0065 static inline u32 READCFG32(u32 addr)
0066 {
0067     return *(u32 *) (cfg_space + (addr & ~3));
0068 }
0069
0070 static inline void WRITECFG32(u32 addr, u32 data)
0071 {
0072     *(u32 *) (cfg_space + (addr & ~3)) = data;
0073 }
0074
0075 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0076 {
0077     return dev->irq;
0078 }
0079
0080 /* Do platform specific device initialization at pci_enable_device() time */
0081 int pcibios_plat_dev_init(struct pci_dev *dev)
0082 {
0083     return 0;
0084 }
0085
0086 /*
0087  * Some checks before doing config cycles:
0088  * In PCI Device Mode, hide everything on bus 0 except the LDT host
0089  * bridge.  Otherwise, access is controlled by bridge MasterEn bits.
0090  */
0091 static int sb1250_pci_can_access(struct pci_bus *bus, int devfn)
0092 {
0093     u32 devno;
0094
0095     if (!(sb1250_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
0096         return 0;
0097
0098     if (bus->number == 0) {
0099         devno = PCI_SLOT(devfn);
0100         if (devno == LDT_BRIDGE_DEVICE)
0101             return (sb1250_bus_status & LDT_BUS_ENABLED) != 0;
0102         else if (sb1250_bus_status & PCI_DEVICE_MODE)
0103             return 0;
0104         else
0105             return 1;
0106     } else
0107         return 1;
0108 }
0109
0110 /*
0111  * Read/write access functions for various sizes of values
0112  * in config space.  Return all 1's for disallowed accesses
0113  * for a kludgy but adequate simulation of master aborts.
0114  */
0115
0116 static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn,
0117                    int where, int size, u32 * val)
0118 {
0119     u32 data = 0;
0120
0121     if ((size == 2) && (where & 1))
0122         return PCIBIOS_BAD_REGISTER_NUMBER;
0123     else if ((size == 4) && (where & 3))
0124         return PCIBIOS_BAD_REGISTER_NUMBER;
0125
0126     if (sb1250_pci_can_access(bus, devfn))
0127         data = READCFG32(CFGADDR(bus, devfn, where));
0128     else
0129         data = 0xFFFFFFFF;
0130
0131     if (size == 1)
0132         *val = (data >> ((where & 3) << 3)) & 0xff;
0133     else if (size == 2)
0134         *val = (data >> ((where & 3) << 3)) & 0xffff;
0135     else
0136         *val = data;
0137
0138     return PCIBIOS_SUCCESSFUL;
0139 }
0140
0141 static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn,
0142                 int where, int size, u32 val)
0143 {
0144     u32 cfgaddr = CFGADDR(bus, devfn, where);
0145     u32 data = 0;
0146
0147     if ((size == 2) && (where & 1))
0148         return PCIBIOS_BAD_REGISTER_NUMBER;
0149     else if ((size == 4) && (where & 3))
0150         return PCIBIOS_BAD_REGISTER_NUMBER;
0151
0152     if (!sb1250_pci_can_access(bus, devfn))
0153         return PCIBIOS_BAD_REGISTER_NUMBER;
0154
0155     data = READCFG32(cfgaddr);
0156
0157     if (size == 1)
0158         data = (data & ~(0xff << ((where & 3) << 3))) |
0159             (val << ((where & 3) << 3));
0160     else if (size == 2)
0161         data = (data & ~(0xffff << ((where & 3) << 3))) |
0162             (val << ((where & 3) << 3));
0163     else
0164         data = val;
0165
0166     WRITECFG32(cfgaddr, data);
0167
0168     return PCIBIOS_SUCCESSFUL;
0169 }
0170
0171 struct pci_ops sb1250_pci_ops = {
0172     .read   = sb1250_pcibios_read,
0173     .write  = sb1250_pcibios_write,
0174 };
0175
0176 static struct resource sb1250_mem_resource = {
0177     .name   = "SB1250 PCI MEM",
0178     .start  = 0x40000000UL,
0179     .end    = 0x5fffffffUL,
0180     .flags  = IORESOURCE_MEM,
0181 };
0182
0183 static struct resource sb1250_io_resource = {
0184     .name   = "SB1250 PCI I/O",
0185     .start  = 0x00000000UL,
0186     .end    = 0x01ffffffUL,
0187     .flags  = IORESOURCE_IO,
0188 };
0189
0190 struct pci_controller sb1250_controller = {
0191     .pci_ops    = &sb1250_pci_ops,
0192     .mem_resource   = &sb1250_mem_resource,
0193     .io_resource    = &sb1250_io_resource,
0194 };
0195
0196 static int __init sb1250_pcibios_init(void)
0197 {
0198     void __iomem *io_map_base;
0199     uint32_t cmdreg;
0200     uint64_t reg;
0201
0202     /* CFE will assign PCI resources */
0203     pci_set_flags(PCI_PROBE_ONLY);
0204
0205     /* Avoid ISA compat ranges.  */
0206     PCIBIOS_MIN_IO = 0x00008000UL;
0207     PCIBIOS_MIN_MEM = 0x01000000UL;
0208
0209     /* Set I/O resource limits.  */
0210     ioport_resource.end = 0x01ffffffUL; /* 32MB accessible by sb1250 */
0211     iomem_resource.end = 0xffffffffUL;  /* no HT support yet */
0212
0213     cfg_space =
0214         ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024);
0215
0216     /*
0217      * See if the PCI bus has been configured by the firmware.
0218      */
0219     reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
0220     if (!(reg & M_SYS_PCI_HOST)) {
0221         sb1250_bus_status |= PCI_DEVICE_MODE;
0222     } else {
0223         cmdreg =
0224             READCFG32(CFGOFFSET
0225                   (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
0226                    PCI_COMMAND));
0227         if (!(cmdreg & PCI_COMMAND_MASTER)) {
0228             printk
0229                 ("PCI: Skipping PCI probe.  Bus is not initialized.\n");
0230             iounmap(cfg_space);
0231             return 0;
0232         }
0233         sb1250_bus_status |= PCI_BUS_ENABLED;
0234     }
0235
0236     /*
0237      * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
0238      * space.  Use "match bytes" policy to make everything look
0239      * little-endian.  So, you need to also set
0240      * CONFIG_SWAP_IO_SPACE, but this is the combination that
0241      * works correctly with most of Linux's drivers.
0242      * XXX ehs: Should this happen in PCI Device mode?
0243      */
0244     io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024);
0245     sb1250_controller.io_map_base = (unsigned long)io_map_base;
0246     set_io_port_base((unsigned long)io_map_base);
0247
0248 #ifdef CONFIG_SIBYTE_HAS_LDT
0249     /*
0250      * Also check the LDT bridge's enable, just in case we didn't
0251      * initialize that one.
0252      */
0253
0254     cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(LDT_BRIDGE_DEVICE, 0),
0255                      PCI_COMMAND));
0256     if (cmdreg & PCI_COMMAND_MASTER) {
0257         sb1250_bus_status |= LDT_BUS_ENABLED;
0258
0259         /*
0260          * Need bits 23:16 to convey vector number.  Note that
0261          * this consumes 4MB of kernel-mapped memory
0262          * (Kseg2/Kseg3) for 32-bit kernel.
0263          */
0264         ldt_eoi_space = (unsigned long)
0265             ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES,
0266                 4 * 1024 * 1024);
0267     }
0268 #endif
0269
0270     register_pci_controller(&sb1250_controller);
0271
0272 #ifdef CONFIG_VGA_CONSOLE
0273     console_lock();
0274     do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1);
0275     console_unlock();
0276 #endif
0277     return 0;
0278 }
0279 arch_initcall(sb1250_pcibios_init);