mips/pci/pci-rt3883.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Ralink RT3662/RT3883 SoC PCI support
0004  *
0005  *  Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
0006  *
0007  *  Parts of this file are based on Ralink's 2.6.21 BSP
0008  */
0009
0010 #include <linux/types.h>
0011 #include <linux/pci.h>
0012 #include <linux/io.h>
0013 #include <linux/init.h>
0014 #include <linux/delay.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/irqdomain.h>
0017 #include <linux/of.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/of_pci.h>
0020 #include <linux/platform_device.h>
0021
0022 #include <asm/mach-ralink/rt3883.h>
0023 #include <asm/mach-ralink/ralink_regs.h>
0024
0025 #define RT3883_MEMORY_BASE      0x00000000
0026 #define RT3883_MEMORY_SIZE      0x02000000
0027
0028 #define RT3883_PCI_REG_PCICFG       0x00
0029 #define   RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
0030 #define   RT3883_PCICFG_P2P_BR_DEVNUM_S 16
0031 #define   RT3883_PCICFG_PCIRST      BIT(1)
0032 #define RT3883_PCI_REG_PCIRAW       0x04
0033 #define RT3883_PCI_REG_PCIINT       0x08
0034 #define RT3883_PCI_REG_PCIENA       0x0c
0035
0036 #define RT3883_PCI_REG_CFGADDR      0x20
0037 #define RT3883_PCI_REG_CFGDATA      0x24
0038 #define RT3883_PCI_REG_MEMBASE      0x28
0039 #define RT3883_PCI_REG_IOBASE       0x2c
0040 #define RT3883_PCI_REG_ARBCTL       0x80
0041
0042 #define RT3883_PCI_REG_BASE(_x)     (0x1000 + (_x) * 0x1000)
0043 #define RT3883_PCI_REG_BAR0SETUP(_x)    (RT3883_PCI_REG_BASE((_x)) + 0x10)
0044 #define RT3883_PCI_REG_IMBASEBAR0(_x)   (RT3883_PCI_REG_BASE((_x)) + 0x18)
0045 #define RT3883_PCI_REG_ID(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x30)
0046 #define RT3883_PCI_REG_CLASS(_x)    (RT3883_PCI_REG_BASE((_x)) + 0x34)
0047 #define RT3883_PCI_REG_SUBID(_x)    (RT3883_PCI_REG_BASE((_x)) + 0x38)
0048 #define RT3883_PCI_REG_STATUS(_x)   (RT3883_PCI_REG_BASE((_x)) + 0x50)
0049
0050 #define RT3883_PCI_MODE_NONE    0
0051 #define RT3883_PCI_MODE_PCI BIT(0)
0052 #define RT3883_PCI_MODE_PCIE    BIT(1)
0053 #define RT3883_PCI_MODE_BOTH    (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
0054
0055 #define RT3883_PCI_IRQ_COUNT    32
0056
0057 #define RT3883_P2P_BR_DEVNUM    1
0058
0059 struct rt3883_pci_controller {
0060     void __iomem *base;
0061
0062     struct device_node *intc_of_node;
0063     struct irq_domain *irq_domain;
0064
0065     struct pci_controller pci_controller;
0066     struct resource io_res;
0067     struct resource mem_res;
0068
0069     bool pcie_ready;
0070 };
0071
0072 static inline struct rt3883_pci_controller *
0073 pci_bus_to_rt3883_controller(struct pci_bus *bus)
0074 {
0075     struct pci_controller *hose;
0076
0077     hose = (struct pci_controller *) bus->sysdata;
0078     return container_of(hose, struct rt3883_pci_controller, pci_controller);
0079 }
0080
0081 static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
0082                  unsigned reg)
0083 {
0084     return ioread32(rpc->base + reg);
0085 }
0086
0087 static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
0088                   u32 val, unsigned reg)
0089 {
0090     iowrite32(val, rpc->base + reg);
0091 }
0092
0093 static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
0094                      unsigned int func, unsigned int where)
0095 {
0096     return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
0097            0x80000000;
0098 }
0099
0100 static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
0101                    unsigned bus, unsigned slot,
0102                    unsigned func, unsigned reg)
0103 {
0104     u32 address;
0105
0106     address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
0107
0108     rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
0109
0110     return rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
0111 }
0112
0113 static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
0114                  unsigned bus, unsigned slot,
0115                  unsigned func, unsigned reg, u32 val)
0116 {
0117     u32 address;
0118
0119     address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
0120
0121     rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
0122     rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
0123 }
0124
0125 static void rt3883_pci_irq_handler(struct irq_desc *desc)
0126 {
0127     struct rt3883_pci_controller *rpc;
0128     u32 pending;
0129
0130     rpc = irq_desc_get_handler_data(desc);
0131
0132     pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
0133           rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
0134
0135     if (!pending) {
0136         spurious_interrupt();
0137         return;
0138     }
0139
0140     while (pending) {
0141         unsigned bit = __ffs(pending);
0142
0143         generic_handle_domain_irq(rpc->irq_domain, bit);
0144
0145         pending &= ~BIT(bit);
0146     }
0147 }
0148
0149 static void rt3883_pci_irq_unmask(struct irq_data *d)
0150 {
0151     struct rt3883_pci_controller *rpc;
0152     u32 t;
0153
0154     rpc = irq_data_get_irq_chip_data(d);
0155
0156     t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
0157     rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
0158     /* flush write */
0159     rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
0160 }
0161
0162 static void rt3883_pci_irq_mask(struct irq_data *d)
0163 {
0164     struct rt3883_pci_controller *rpc;
0165     u32 t;
0166
0167     rpc = irq_data_get_irq_chip_data(d);
0168
0169     t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
0170     rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
0171     /* flush write */
0172     rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
0173 }
0174
0175 static struct irq_chip rt3883_pci_irq_chip = {
0176     .name       = "RT3883 PCI",
0177     .irq_mask   = rt3883_pci_irq_mask,
0178     .irq_unmask = rt3883_pci_irq_unmask,
0179     .irq_mask_ack   = rt3883_pci_irq_mask,
0180 };
0181
0182 static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
0183                   irq_hw_number_t hw)
0184 {
0185     irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
0186     irq_set_chip_data(irq, d->host_data);
0187
0188     return 0;
0189 }
0190
0191 static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
0192     .map = rt3883_pci_irq_map,
0193     .xlate = irq_domain_xlate_onecell,
0194 };
0195
0196 static int rt3883_pci_irq_init(struct device *dev,
0197                    struct rt3883_pci_controller *rpc)
0198 {
0199     int irq;
0200
0201     irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
0202     if (irq == 0) {
0203         dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node);
0204         return -EINVAL;
0205     }
0206
0207     /* disable all interrupts */
0208     rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
0209
0210     rpc->irq_domain =
0211         irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
0212                       &rt3883_pci_irq_domain_ops,
0213                       rpc);
0214     if (!rpc->irq_domain) {
0215         dev_err(dev, "unable to add IRQ domain\n");
0216         return -ENODEV;
0217     }
0218
0219     irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc);
0220
0221     return 0;
0222 }
0223
0224 static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
0225                   int where, int size, u32 *val)
0226 {
0227     struct rt3883_pci_controller *rpc;
0228     u32 address;
0229     u32 data;
0230
0231     rpc = pci_bus_to_rt3883_controller(bus);
0232
0233     if (!rpc->pcie_ready && bus->number == 1)
0234         return PCIBIOS_DEVICE_NOT_FOUND;
0235
0236     address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
0237                      PCI_FUNC(devfn), where);
0238
0239     rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
0240     data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
0241
0242     switch (size) {
0243     case 1:
0244         *val = (data >> ((where & 3) << 3)) & 0xff;
0245         break;
0246     case 2:
0247         *val = (data >> ((where & 3) << 3)) & 0xffff;
0248         break;
0249     case 4:
0250         *val = data;
0251         break;
0252     }
0253
0254     return PCIBIOS_SUCCESSFUL;
0255 }
0256
0257 static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
0258                    int where, int size, u32 val)
0259 {
0260     struct rt3883_pci_controller *rpc;
0261     u32 address;
0262     u32 data;
0263
0264     rpc = pci_bus_to_rt3883_controller(bus);
0265
0266     if (!rpc->pcie_ready && bus->number == 1)
0267         return PCIBIOS_DEVICE_NOT_FOUND;
0268
0269     address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
0270                      PCI_FUNC(devfn), where);
0271
0272     rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
0273     data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
0274
0275     switch (size) {
0276     case 1:
0277         data = (data & ~(0xff << ((where & 3) << 3))) |
0278                (val << ((where & 3) << 3));
0279         break;
0280     case 2:
0281         data = (data & ~(0xffff << ((where & 3) << 3))) |
0282                (val << ((where & 3) << 3));
0283         break;
0284     case 4:
0285         data = val;
0286         break;
0287     }
0288
0289     rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
0290
0291     return PCIBIOS_SUCCESSFUL;
0292 }
0293
0294 static struct pci_ops rt3883_pci_ops = {
0295     .read   = rt3883_pci_config_read,
0296     .write  = rt3883_pci_config_write,
0297 };
0298
0299 static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
0300 {
0301     u32 syscfg1;
0302     u32 rstctrl;
0303     u32 clkcfg1;
0304     u32 t;
0305
0306     rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
0307     syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
0308     clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
0309
0310     if (mode & RT3883_PCI_MODE_PCIE) {
0311         rstctrl |= RT3883_RSTCTRL_PCIE;
0312         rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
0313
0314         /* setup PCI PAD drive mode */
0315         syscfg1 &= ~(0x30);
0316         syscfg1 |= (2 << 4);
0317         rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
0318
0319         t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
0320         t &= ~BIT(31);
0321         rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
0322
0323         t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
0324         t &= 0x80ffffff;
0325         rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
0326
0327         t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
0328         t |= 0xa << 24;
0329         rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
0330
0331         t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
0332         t |= BIT(31);
0333         rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
0334
0335         msleep(50);
0336
0337         rstctrl &= ~RT3883_RSTCTRL_PCIE;
0338         rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
0339     }
0340
0341     syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
0342
0343     clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
0344
0345     if (mode & RT3883_PCI_MODE_PCI) {
0346         clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
0347         rstctrl &= ~RT3883_RSTCTRL_PCI;
0348     }
0349
0350     if (mode & RT3883_PCI_MODE_PCIE) {
0351         clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
0352         rstctrl &= ~RT3883_RSTCTRL_PCIE;
0353     }
0354
0355     rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
0356     rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
0357     rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
0358
0359     msleep(500);
0360
0361     /*
0362      * setup the device number of the P2P bridge
0363      * and de-assert the reset line
0364      */
0365     t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
0366     rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
0367
0368     /* flush write */
0369     rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
0370     msleep(500);
0371
0372     if (mode & RT3883_PCI_MODE_PCIE) {
0373         msleep(500);
0374
0375         t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
0376
0377         rpc->pcie_ready = t & BIT(0);
0378
0379         if (!rpc->pcie_ready) {
0380             /* reset the PCIe block */
0381             t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
0382             t |= RT3883_RSTCTRL_PCIE;
0383             rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
0384             t &= ~RT3883_RSTCTRL_PCIE;
0385             rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
0386
0387             /* turn off PCIe clock */
0388             t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
0389             t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
0390             rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
0391
0392             t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
0393             t &= ~0xf000c080;
0394             rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
0395         }
0396     }
0397
0398     /* enable PCI arbiter */
0399     rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
0400 }
0401
0402 static int rt3883_pci_probe(struct platform_device *pdev)
0403 {
0404     struct rt3883_pci_controller *rpc;
0405     struct device *dev = &pdev->dev;
0406     struct device_node *np = dev->of_node;
0407     struct resource *res;
0408     struct device_node *child;
0409     u32 val;
0410     int err;
0411     int mode;
0412
0413     rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
0414     if (!rpc)
0415         return -ENOMEM;
0416
0417     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0418     rpc->base = devm_ioremap_resource(dev, res);
0419     if (IS_ERR(rpc->base))
0420         return PTR_ERR(rpc->base);
0421
0422     /* find the interrupt controller child node */
0423     for_each_child_of_node(np, child) {
0424         if (of_get_property(child, "interrupt-controller", NULL)) {
0425             rpc->intc_of_node = child;
0426             break;
0427         }
0428     }
0429
0430     if (!rpc->intc_of_node) {
0431         dev_err(dev, "%pOF has no %s child node",
0432             np, "interrupt controller");
0433         return -EINVAL;
0434     }
0435
0436     /* find the PCI host bridge child node */
0437     for_each_child_of_node(np, child) {
0438         if (of_node_is_type(child, "pci")) {
0439             rpc->pci_controller.of_node = child;
0440             break;
0441         }
0442     }
0443
0444     if (!rpc->pci_controller.of_node) {
0445         dev_err(dev, "%pOF has no %s child node",
0446             np, "PCI host bridge");
0447         err = -EINVAL;
0448         goto err_put_intc_node;
0449     }
0450
0451     mode = RT3883_PCI_MODE_NONE;
0452     for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
0453         int devfn;
0454
0455         if (!of_node_is_type(child, "pci"))
0456             continue;
0457
0458         devfn = of_pci_get_devfn(child);
0459         if (devfn < 0)
0460             continue;
0461
0462         switch (PCI_SLOT(devfn)) {
0463         case 1:
0464             mode |= RT3883_PCI_MODE_PCIE;
0465             break;
0466
0467         case 17:
0468         case 18:
0469             mode |= RT3883_PCI_MODE_PCI;
0470             break;
0471         }
0472     }
0473
0474     if (mode == RT3883_PCI_MODE_NONE) {
0475         dev_err(dev, "unable to determine PCI mode\n");
0476         err = -EINVAL;
0477         goto err_put_hb_node;
0478     }
0479
0480     dev_info(dev, "mode:%s%s\n",
0481          (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
0482          (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
0483
0484     rt3883_pci_preinit(rpc, mode);
0485
0486     rpc->pci_controller.pci_ops = &rt3883_pci_ops;
0487     rpc->pci_controller.io_resource = &rpc->io_res;
0488     rpc->pci_controller.mem_resource = &rpc->mem_res;
0489
0490     /* Load PCI I/O and memory resources from DT */
0491     pci_load_of_ranges(&rpc->pci_controller,
0492                rpc->pci_controller.of_node);
0493
0494     rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
0495     rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
0496
0497     ioport_resource.start = rpc->io_res.start;
0498     ioport_resource.end = rpc->io_res.end;
0499
0500     /* PCI */
0501     rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
0502     rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
0503     rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
0504     rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
0505     rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
0506
0507     /* PCIe */
0508     rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
0509     rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
0510     rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
0511     rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
0512     rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
0513
0514     err = rt3883_pci_irq_init(dev, rpc);
0515     if (err)
0516         goto err_put_hb_node;
0517
0518     /* PCIe */
0519     val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
0520     val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
0521     rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
0522
0523     /* PCI */
0524     val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
0525     val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
0526     rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
0527
0528     if (mode == RT3883_PCI_MODE_PCIE) {
0529         rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
0530         rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
0531
0532         rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
0533                        PCI_BASE_ADDRESS_0,
0534                        RT3883_MEMORY_BASE);
0535         /* flush write */
0536         rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
0537                       PCI_BASE_ADDRESS_0);
0538     } else {
0539         rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
0540                        PCI_IO_BASE, 0x00000101);
0541     }
0542
0543     register_pci_controller(&rpc->pci_controller);
0544
0545     return 0;
0546
0547 err_put_hb_node:
0548     of_node_put(rpc->pci_controller.of_node);
0549 err_put_intc_node:
0550     of_node_put(rpc->intc_of_node);
0551     return err;
0552 }
0553
0554 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0555 {
0556     return of_irq_parse_and_map_pci(dev, slot, pin);
0557 }
0558
0559 int pcibios_plat_dev_init(struct pci_dev *dev)
0560 {
0561     return 0;
0562 }
0563
0564 static const struct of_device_id rt3883_pci_ids[] = {
0565     { .compatible = "ralink,rt3883-pci" },
0566     {},
0567 };
0568
0569 static struct platform_driver rt3883_pci_driver = {
0570     .probe = rt3883_pci_probe,
0571     .driver = {
0572         .name = "rt3883-pci",
0573         .of_match_table = of_match_ptr(rt3883_pci_ids),
0574     },
0575 };
0576
0577 static int __init rt3883_pci_init(void)
0578 {
0579     return platform_driver_register(&rt3883_pci_driver);
0580 }
0581
0582 postcore_initcall(rt3883_pci_init);