mips/pci/pci-rt2880.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Ralink RT288x SoC PCI register definitions
0004  *
0005  *  Copyright (C) 2009 John Crispin <john@phrozen.org>
0006  *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
0007  *
0008  *  Parts of this file are based on Ralink's 2.6.21 BSP
0009  */
0010
0011 #include <linux/delay.h>
0012 #include <linux/types.h>
0013 #include <linux/pci.h>
0014 #include <linux/io.h>
0015 #include <linux/init.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/of_pci.h>
0019
0020 #include <asm/mach-ralink/rt288x.h>
0021
0022 #define RT2880_PCI_BASE     0x00440000
0023 #define RT288X_CPU_IRQ_PCI  4
0024
0025 #define RT2880_PCI_MEM_BASE 0x20000000
0026 #define RT2880_PCI_MEM_SIZE 0x10000000
0027 #define RT2880_PCI_IO_BASE  0x00460000
0028 #define RT2880_PCI_IO_SIZE  0x00010000
0029
0030 #define RT2880_PCI_REG_PCICFG_ADDR  0x00
0031 #define RT2880_PCI_REG_PCIMSK_ADDR  0x0c
0032 #define RT2880_PCI_REG_BAR0SETUP_ADDR   0x10
0033 #define RT2880_PCI_REG_IMBASEBAR0_ADDR  0x18
0034 #define RT2880_PCI_REG_CONFIG_ADDR  0x20
0035 #define RT2880_PCI_REG_CONFIG_DATA  0x24
0036 #define RT2880_PCI_REG_MEMBASE      0x28
0037 #define RT2880_PCI_REG_IOBASE       0x2c
0038 #define RT2880_PCI_REG_ID       0x30
0039 #define RT2880_PCI_REG_CLASS        0x34
0040 #define RT2880_PCI_REG_SUBID        0x38
0041 #define RT2880_PCI_REG_ARBCTL       0x80
0042
0043 static void __iomem *rt2880_pci_base;
0044
0045 static u32 rt2880_pci_reg_read(u32 reg)
0046 {
0047     return readl(rt2880_pci_base + reg);
0048 }
0049
0050 static void rt2880_pci_reg_write(u32 val, u32 reg)
0051 {
0052     writel(val, rt2880_pci_base + reg);
0053 }
0054
0055 static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
0056                      unsigned int func, unsigned int where)
0057 {
0058     return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
0059         0x80000000);
0060 }
0061
0062 static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
0063                   int where, int size, u32 *val)
0064 {
0065     u32 address;
0066     u32 data;
0067
0068     address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
0069                      PCI_FUNC(devfn), where);
0070
0071     rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
0072     data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
0073
0074     switch (size) {
0075     case 1:
0076         *val = (data >> ((where & 3) << 3)) & 0xff;
0077         break;
0078     case 2:
0079         *val = (data >> ((where & 3) << 3)) & 0xffff;
0080         break;
0081     case 4:
0082         *val = data;
0083         break;
0084     }
0085
0086     return PCIBIOS_SUCCESSFUL;
0087 }
0088
0089 static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
0090                    int where, int size, u32 val)
0091 {
0092     u32 address;
0093     u32 data;
0094
0095     address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
0096                      PCI_FUNC(devfn), where);
0097
0098     rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
0099     data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
0100
0101     switch (size) {
0102     case 1:
0103         data = (data & ~(0xff << ((where & 3) << 3))) |
0104                (val << ((where & 3) << 3));
0105         break;
0106     case 2:
0107         data = (data & ~(0xffff << ((where & 3) << 3))) |
0108                (val << ((where & 3) << 3));
0109         break;
0110     case 4:
0111         data = val;
0112         break;
0113     }
0114
0115     rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
0116
0117     return PCIBIOS_SUCCESSFUL;
0118 }
0119
0120 static struct pci_ops rt2880_pci_ops = {
0121     .read   = rt2880_pci_config_read,
0122     .write  = rt2880_pci_config_write,
0123 };
0124
0125 static struct resource rt2880_pci_mem_resource = {
0126     .name   = "PCI MEM space",
0127     .start  = RT2880_PCI_MEM_BASE,
0128     .end    = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
0129     .flags  = IORESOURCE_MEM,
0130 };
0131
0132 static struct resource rt2880_pci_io_resource = {
0133     .name   = "PCI IO space",
0134     .start  = RT2880_PCI_IO_BASE,
0135     .end    = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
0136     .flags  = IORESOURCE_IO,
0137 };
0138
0139 static struct pci_controller rt2880_pci_controller = {
0140     .pci_ops    = &rt2880_pci_ops,
0141     .mem_resource   = &rt2880_pci_mem_resource,
0142     .io_resource    = &rt2880_pci_io_resource,
0143 };
0144
0145 static inline u32 rt2880_pci_read_u32(unsigned long reg)
0146 {
0147     u32 address;
0148     u32 ret;
0149
0150     address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
0151
0152     rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
0153     ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
0154
0155     return ret;
0156 }
0157
0158 static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
0159 {
0160     u32 address;
0161
0162     address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
0163
0164     rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
0165     rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
0166 }
0167
0168 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0169 {
0170     int irq = -1;
0171
0172     if (dev->bus->number != 0)
0173         return irq;
0174
0175     switch (PCI_SLOT(dev->devfn)) {
0176     case 0x00:
0177         break;
0178     case 0x11:
0179         irq = RT288X_CPU_IRQ_PCI;
0180         break;
0181     default:
0182         pr_err("%s:%s[%d] trying to alloc unknown pci irq\n",
0183                __FILE__, __func__, __LINE__);
0184         BUG();
0185         break;
0186     }
0187
0188     return irq;
0189 }
0190
0191 static int rt288x_pci_probe(struct platform_device *pdev)
0192 {
0193     void __iomem *io_map_base;
0194
0195     rt2880_pci_base = ioremap(RT2880_PCI_BASE, PAGE_SIZE);
0196
0197     io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
0198     rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
0199     set_io_port_base((unsigned long) io_map_base);
0200
0201     ioport_resource.start = RT2880_PCI_IO_BASE;
0202     ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
0203
0204     rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
0205     udelay(1);
0206
0207     rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
0208     rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
0209     rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
0210     rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
0211     rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
0212     rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
0213     rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
0214     rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
0215     rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
0216
0217     rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
0218     (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
0219
0220     rt2880_pci_controller.of_node = pdev->dev.of_node;
0221
0222     register_pci_controller(&rt2880_pci_controller);
0223     return 0;
0224 }
0225
0226 int pcibios_plat_dev_init(struct pci_dev *dev)
0227 {
0228     static bool slot0_init;
0229
0230     /*
0231      * Nobody seems to initialize slot 0, but this platform requires it, so
0232      * do it once when some other slot is being enabled. The PCI subsystem
0233      * should configure other slots properly, so no need to do anything
0234      * special for those.
0235      */
0236     if (!slot0_init && dev->bus->number == 0) {
0237         u16 cmd;
0238         u32 bar0;
0239
0240         slot0_init = true;
0241
0242         pci_bus_write_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0,
0243                        0x08000000);
0244         pci_bus_read_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0,
0245                       &bar0);
0246
0247         pci_bus_read_config_word(dev->bus, 0, PCI_COMMAND, &cmd);
0248         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
0249         pci_bus_write_config_word(dev->bus, 0, PCI_COMMAND, cmd);
0250     }
0251
0252     return 0;
0253 }
0254
0255 static const struct of_device_id rt288x_pci_match[] = {
0256     { .compatible = "ralink,rt288x-pci" },
0257     {},
0258 };
0259
0260 static struct platform_driver rt288x_pci_driver = {
0261     .probe = rt288x_pci_probe,
0262     .driver = {
0263         .name = "rt288x-pci",
0264         .of_match_table = rt288x_pci_match,
0265     },
0266 };
0267
0268 int __init pcibios_init(void)
0269 {
0270     int ret = platform_driver_register(&rt288x_pci_driver);
0271
0272     if (ret)
0273         pr_info("rt288x-pci: Error registering platform driver!");
0274
0275     return ret;
0276 }
0277
0278 arch_initcall(pcibios_init);