mips/pci/pci-rc32434.c

0001 /*
0002  *  BRIEF MODULE DESCRIPTION
0003  *     PCI initialization for IDT EB434 board
0004  *
0005  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
0006  *
0007  *  This program is free software; you can redistribute  it and/or modify it
0008  *  under  the terms of  the GNU General  Public License as published by the
0009  *  Free Software Foundation;  either version 2 of the  License, or (at your
0010  *  option) any later version.
0011  *
0012  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0013  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0014  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0015  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0016  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0017  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0018  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0019  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0020  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0021  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0022  *
0023  *  You should have received a copy of the  GNU General Public License along
0024  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0025  *  675 Mass Ave, Cambridge, MA 02139, USA.
0026  */
0027
0028 #include <linux/types.h>
0029 #include <linux/pci.h>
0030 #include <linux/kernel.h>
0031 #include <linux/init.h>
0032
0033 #include <asm/mach-rc32434/rc32434.h>
0034 #include <asm/mach-rc32434/pci.h>
0035
0036 #define PCI_ACCESS_READ  0
0037 #define PCI_ACCESS_WRITE 1
0038
0039 /* define an unsigned array for the PCI registers */
0040 static unsigned int korina_cnfg_regs[25] = {
0041     KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
0042     KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
0043     KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
0044     KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
0045     KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
0046     KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
0047 };
0048 static struct resource rc32434_res_pci_mem1;
0049 static struct resource rc32434_res_pci_mem2;
0050
0051 static struct resource rc32434_res_pci_mem1 = {
0052     .name = "PCI MEM1",
0053     .start = 0x50000000,
0054     .end = 0x5FFFFFFF,
0055     .flags = IORESOURCE_MEM,
0056     .sibling = NULL,
0057     .child = &rc32434_res_pci_mem2
0058 };
0059
0060 static struct resource rc32434_res_pci_mem2 = {
0061     .name = "PCI Mem2",
0062     .start = 0x60000000,
0063     .end = 0x6FFFFFFF,
0064     .flags = IORESOURCE_MEM,
0065     .parent = &rc32434_res_pci_mem1,
0066     .sibling = NULL,
0067     .child = NULL
0068 };
0069
0070 static struct resource rc32434_res_pci_io1 = {
0071     .name = "PCI I/O1",
0072     .start = 0x18800000,
0073     .end = 0x188FFFFF,
0074     .flags = IORESOURCE_IO,
0075 };
0076
0077 extern struct pci_ops rc32434_pci_ops;
0078
0079 #define PCI_MEM1_START  PCI_ADDR_START
0080 #define PCI_MEM1_END    (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1)
0081 #define PCI_MEM2_START  (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
0082 #define PCI_MEM2_END    (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)  - 1)
0083 #define PCI_IO1_START   (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
0084 #define PCI_IO1_END                         \
0085     (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
0086 #define PCI_IO2_START                           \
0087     (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
0088 #define PCI_IO2_END                         \
0089     (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
0090
0091 struct pci_controller rc32434_controller2;
0092
0093 struct pci_controller rc32434_controller = {
0094     .pci_ops = &rc32434_pci_ops,
0095     .mem_resource = &rc32434_res_pci_mem1,
0096     .io_resource = &rc32434_res_pci_io1,
0097     .mem_offset = 0,
0098     .io_offset = 0,
0099
0100 };
0101
0102 #ifdef __MIPSEB__
0103 #define PCI_ENDIAN_FLAG PCILBAC_sb_m
0104 #else
0105 #define PCI_ENDIAN_FLAG 0
0106 #endif
0107
0108 static int __init rc32434_pcibridge_init(void)
0109 {
0110     unsigned int pcicvalue, pcicdata = 0;
0111     unsigned int dummyread, pcicntlval;
0112     int loopCount;
0113     unsigned int pci_config_addr;
0114
0115     pcicvalue = rc32434_pci->pcic;
0116     pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN;
0117     if (!((pcicvalue == PCIM_H_EA) ||
0118           (pcicvalue == PCIM_H_IA_FIX) ||
0119           (pcicvalue == PCIM_H_IA_RR))) {
0120         pr_err("PCI init error!!!\n");
0121         /* Not in Host Mode, return ERROR */
0122         return -1;
0123     }
0124     /* Enables the Idle Grant mode, Arbiter Parking */
0125     pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN);
0126     rc32434_pci->pcic = pcicdata;   /* Enable the PCI bus Interface */
0127     /* Zero out the PCI status & PCI Status Mask */
0128     for (;;) {
0129         pcicdata = rc32434_pci->pcis;
0130         if (!(pcicdata & PCI_STAT_RIP))
0131             break;
0132     }
0133
0134     rc32434_pci->pcis = 0;
0135     rc32434_pci->pcism = 0xFFFFFFFF;
0136     /* Zero out the PCI decoupled registers */
0137     rc32434_pci->pcidac = 0;    /*
0138                      * disable PCI decoupled accesses at
0139                      * initialization
0140                      */
0141     rc32434_pci->pcidas = 0;    /* clear the status */
0142     rc32434_pci->pcidasm = 0x0000007F;  /* Mask all the interrupts */
0143     /* Mask PCI Messaging Interrupts */
0144     rc32434_pci_msg->pciiic = 0;
0145     rc32434_pci_msg->pciiim = 0xFFFFFFFF;
0146     rc32434_pci_msg->pciioic = 0;
0147     rc32434_pci_msg->pciioim = 0;
0148
0149
0150     /* Setup PCILB0 as Memory Window */
0151     rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START);
0152
0153     /* setup the PCI map address as same as the local address */
0154
0155     rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START);
0156
0157
0158     /* Setup PCILBA1 as MEM */
0159     rc32434_pci->pcilba[0].control =
0160         (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
0161     dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */
0162     rc32434_pci->pcilba[1].address = 0x60000000;
0163     rc32434_pci->pcilba[1].mapping = 0x60000000;
0164
0165     /* setup PCILBA2 as IO Window */
0166     rc32434_pci->pcilba[1].control =
0167         (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
0168     dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */
0169     rc32434_pci->pcilba[2].address = 0x18C00000;
0170     rc32434_pci->pcilba[2].mapping = 0x18FFFFFF;
0171
0172     /* setup PCILBA2 as IO Window */
0173     rc32434_pci->pcilba[2].control =
0174         (((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
0175     dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */
0176
0177     /* Setup PCILBA3 as IO Window */
0178     rc32434_pci->pcilba[3].address = 0x18800000;
0179     rc32434_pci->pcilba[3].mapping = 0x18800000;
0180     rc32434_pci->pcilba[3].control =
0181         ((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) |
0182          PCI_ENDIAN_FLAG);
0183     dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */
0184
0185     pci_config_addr = (unsigned int) (0x80000004);
0186     for (loopCount = 0; loopCount < 24; loopCount++) {
0187         rc32434_pci->pcicfga = pci_config_addr;
0188         dummyread = rc32434_pci->pcicfga;
0189         rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount];
0190         dummyread = rc32434_pci->pcicfgd;
0191         pci_config_addr += 4;
0192     }
0193     rc32434_pci->pcitc =
0194         (unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) |
0195         ((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT);
0196
0197     pcicntlval = rc32434_pci->pcic;
0198     pcicntlval &= ~PCI_CTL_TNR;
0199     rc32434_pci->pcic = pcicntlval;
0200     pcicntlval = rc32434_pci->pcic;
0201
0202     return 0;
0203 }
0204
0205 static int __init rc32434_pci_init(void)
0206 {
0207     void __iomem *io_map_base;
0208
0209     pr_info("PCI: Initializing PCI\n");
0210
0211     ioport_resource.start = rc32434_res_pci_io1.start;
0212     ioport_resource.end = rc32434_res_pci_io1.end;
0213
0214     rc32434_pcibridge_init();
0215
0216     io_map_base = ioremap(rc32434_res_pci_io1.start,
0217                   resource_size(&rc32434_res_pci_io1));
0218
0219     if (!io_map_base)
0220         return -ENOMEM;
0221
0222     rc32434_controller.io_map_base =
0223         (unsigned long)io_map_base - rc32434_res_pci_io1.start;
0224
0225     register_pci_controller(&rc32434_controller);
0226     rc32434_sync();
0227
0228     return 0;
0229 }
0230
0231 arch_initcall(rc32434_pci_init);