mips/pci/pci-octeon.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2005-2009 Cavium Networks
0007  */
0008 #include <linux/kernel.h>
0009 #include <linux/init.h>
0010 #include <linux/pci.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/time.h>
0013 #include <linux/delay.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/swiotlb.h>
0016
0017 #include <asm/time.h>
0018
0019 #include <asm/octeon/octeon.h>
0020 #include <asm/octeon/cvmx-npi-defs.h>
0021 #include <asm/octeon/cvmx-pci-defs.h>
0022 #include <asm/octeon/pci-octeon.h>
0023
0024 #define USE_OCTEON_INTERNAL_ARBITER
0025
0026 /*
0027  * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
0028  * addresses. Use PCI endian swapping 1 so no address swapping is
0029  * necessary. The Linux io routines will endian swap the data.
0030  */
0031 #define OCTEON_PCI_IOSPACE_BASE     0x80011a0400000000ull
0032 #define OCTEON_PCI_IOSPACE_SIZE     (1ull<<32)
0033
0034 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
0035 #define OCTEON_PCI_MEMSPACE_OFFSET  (0x00011b0000000000ull)
0036
0037 u64 octeon_bar1_pci_phys;
0038
0039 /**
0040  * This is the bit decoding used for the Octeon PCI controller addresses
0041  */
0042 union octeon_pci_address {
0043     uint64_t u64;
0044     struct {
0045         uint64_t upper:2;
0046         uint64_t reserved:13;
0047         uint64_t io:1;
0048         uint64_t did:5;
0049         uint64_t subdid:3;
0050         uint64_t reserved2:4;
0051         uint64_t endian_swap:2;
0052         uint64_t reserved3:10;
0053         uint64_t bus:8;
0054         uint64_t dev:5;
0055         uint64_t func:3;
0056         uint64_t reg:8;
0057     } s;
0058 };
0059
0060 int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
0061 enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
0062
0063 /**
0064  * Map a PCI device to the appropriate interrupt line
0065  *
0066  * @dev:    The Linux PCI device structure for the device to map
0067  * @slot:   The slot number for this device on __BUS 0__. Linux
0068  *       enumerates through all the bridges and figures out the
0069  *       slot on Bus 0 where this device eventually hooks to.
0070  * @pin:    The PCI interrupt pin read from the device, then swizzled
0071  *       as it goes through each bridge.
0072  * Returns Interrupt number for the device
0073  */
0074 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0075 {
0076     if (octeon_pcibios_map_irq)
0077         return octeon_pcibios_map_irq(dev, slot, pin);
0078     else
0079         panic("octeon_pcibios_map_irq not set.");
0080 }
0081
0082
0083 /*
0084  * Called to perform platform specific PCI setup
0085  */
0086 int pcibios_plat_dev_init(struct pci_dev *dev)
0087 {
0088     uint16_t config;
0089     uint32_t dconfig;
0090     int pos;
0091     /*
0092      * Force the Cache line setting to 64 bytes. The standard
0093      * Linux bus scan doesn't seem to set it. Octeon really has
0094      * 128 byte lines, but Intel bridges get really upset if you
0095      * try and set values above 64 bytes. Value is specified in
0096      * 32bit words.
0097      */
0098     pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
0099     /* Set latency timers for all devices */
0100     pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
0101
0102     /* Enable reporting System errors and parity errors on all devices */
0103     /* Enable parity checking and error reporting */
0104     pci_read_config_word(dev, PCI_COMMAND, &config);
0105     config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
0106     pci_write_config_word(dev, PCI_COMMAND, config);
0107
0108     if (dev->subordinate) {
0109         /* Set latency timers on sub bridges */
0110         pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
0111         /* More bridge error detection */
0112         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
0113         config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
0114         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
0115     }
0116
0117     /* Enable the PCIe normal error reporting */
0118     config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
0119     config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
0120     config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
0121     config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
0122     pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
0123
0124     /* Find the Advanced Error Reporting capability */
0125     pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
0126     if (pos) {
0127         /* Clear Uncorrectable Error Status */
0128         pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
0129                       &dconfig);
0130         pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
0131                        dconfig);
0132         /* Enable reporting of all uncorrectable errors */
0133         /* Uncorrectable Error Mask - turned on bits disable errors */
0134         pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
0135         /*
0136          * Leave severity at HW default. This only controls if
0137          * errors are reported as uncorrectable or
0138          * correctable, not if the error is reported.
0139          */
0140         /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
0141         /* Clear Correctable Error Status */
0142         pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
0143         pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
0144         /* Enable reporting of all correctable errors */
0145         /* Correctable Error Mask - turned on bits disable errors */
0146         pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
0147         /* Advanced Error Capabilities */
0148         pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
0149         /* ECRC Generation Enable */
0150         if (config & PCI_ERR_CAP_ECRC_GENC)
0151             config |= PCI_ERR_CAP_ECRC_GENE;
0152         /* ECRC Check Enable */
0153         if (config & PCI_ERR_CAP_ECRC_CHKC)
0154             config |= PCI_ERR_CAP_ECRC_CHKE;
0155         pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
0156         /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
0157         /* Report all errors to the root complex */
0158         pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
0159                        PCI_ERR_ROOT_CMD_COR_EN |
0160                        PCI_ERR_ROOT_CMD_NONFATAL_EN |
0161                        PCI_ERR_ROOT_CMD_FATAL_EN);
0162         /* Clear the Root status register */
0163         pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
0164         pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
0165     }
0166
0167     return 0;
0168 }
0169
0170 /**
0171  * Return the mapping of PCI device number to IRQ line. Each
0172  * character in the return string represents the interrupt
0173  * line for the device at that position. Device 1 maps to the
0174  * first character, etc. The characters A-D are used for PCI
0175  * interrupts.
0176  *
0177  * Returns PCI interrupt mapping
0178  */
0179 const char *octeon_get_pci_interrupts(void)
0180 {
0181     /*
0182      * Returning an empty string causes the interrupts to be
0183      * routed based on the PCI specification. From the PCI spec:
0184      *
0185      * INTA# of Device Number 0 is connected to IRQW on the system
0186      * board.  (Device Number has no significance regarding being
0187      * located on the system board or in a connector.) INTA# of
0188      * Device Number 1 is connected to IRQX on the system
0189      * board. INTA# of Device Number 2 is connected to IRQY on the
0190      * system board. INTA# of Device Number 3 is connected to IRQZ
0191      * on the system board. The table below describes how each
0192      * agent's INTx# lines are connected to the system board
0193      * interrupt lines. The following equation can be used to
0194      * determine to which INTx# signal on the system board a given
0195      * device's INTx# line(s) is connected.
0196      *
0197      * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
0198      * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
0199      * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
0200      * INTD# = 3)
0201      */
0202     if (of_machine_is_compatible("dlink,dsr-500n"))
0203         return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
0204     switch (octeon_bootinfo->board_type) {
0205     case CVMX_BOARD_TYPE_NAO38:
0206         /* This is really the NAC38 */
0207         return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
0208     case CVMX_BOARD_TYPE_EBH3100:
0209     case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
0210     case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
0211         return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
0212     case CVMX_BOARD_TYPE_BBGW_REF:
0213         return "AABCD";
0214     case CVMX_BOARD_TYPE_CUST_DSR1000N:
0215         return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
0216     case CVMX_BOARD_TYPE_THUNDER:
0217     case CVMX_BOARD_TYPE_EBH3000:
0218     default:
0219         return "";
0220     }
0221 }
0222
0223 /**
0224  * Map a PCI device to the appropriate interrupt line
0225  *
0226  * @dev:    The Linux PCI device structure for the device to map
0227  * @slot:   The slot number for this device on __BUS 0__. Linux
0228  *       enumerates through all the bridges and figures out the
0229  *       slot on Bus 0 where this device eventually hooks to.
0230  * @pin:    The PCI interrupt pin read from the device, then swizzled
0231  *       as it goes through each bridge.
0232  * Returns Interrupt number for the device
0233  */
0234 int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
0235                       u8 slot, u8 pin)
0236 {
0237     int irq_num;
0238     const char *interrupts;
0239     int dev_num;
0240
0241     /* Get the board specific interrupt mapping */
0242     interrupts = octeon_get_pci_interrupts();
0243
0244     dev_num = dev->devfn >> 3;
0245     if (dev_num < strlen(interrupts))
0246         irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
0247             OCTEON_IRQ_PCI_INT0;
0248     else
0249         irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
0250     return irq_num;
0251 }
0252
0253
0254 /*
0255  * Read a value from configuration space
0256  */
0257 static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
0258                   int reg, int size, u32 *val)
0259 {
0260     union octeon_pci_address pci_addr;
0261
0262     pci_addr.u64 = 0;
0263     pci_addr.s.upper = 2;
0264     pci_addr.s.io = 1;
0265     pci_addr.s.did = 3;
0266     pci_addr.s.subdid = 1;
0267     pci_addr.s.endian_swap = 1;
0268     pci_addr.s.bus = bus->number;
0269     pci_addr.s.dev = devfn >> 3;
0270     pci_addr.s.func = devfn & 0x7;
0271     pci_addr.s.reg = reg;
0272
0273     switch (size) {
0274     case 4:
0275         *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
0276         return PCIBIOS_SUCCESSFUL;
0277     case 2:
0278         *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
0279         return PCIBIOS_SUCCESSFUL;
0280     case 1:
0281         *val = cvmx_read64_uint8(pci_addr.u64);
0282         return PCIBIOS_SUCCESSFUL;
0283     }
0284     return PCIBIOS_FUNC_NOT_SUPPORTED;
0285 }
0286
0287
0288 /*
0289  * Write a value to PCI configuration space
0290  */
0291 static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
0292                    int reg, int size, u32 val)
0293 {
0294     union octeon_pci_address pci_addr;
0295
0296     pci_addr.u64 = 0;
0297     pci_addr.s.upper = 2;
0298     pci_addr.s.io = 1;
0299     pci_addr.s.did = 3;
0300     pci_addr.s.subdid = 1;
0301     pci_addr.s.endian_swap = 1;
0302     pci_addr.s.bus = bus->number;
0303     pci_addr.s.dev = devfn >> 3;
0304     pci_addr.s.func = devfn & 0x7;
0305     pci_addr.s.reg = reg;
0306
0307     switch (size) {
0308     case 4:
0309         cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
0310         return PCIBIOS_SUCCESSFUL;
0311     case 2:
0312         cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
0313         return PCIBIOS_SUCCESSFUL;
0314     case 1:
0315         cvmx_write64_uint8(pci_addr.u64, val);
0316         return PCIBIOS_SUCCESSFUL;
0317     }
0318     return PCIBIOS_FUNC_NOT_SUPPORTED;
0319 }
0320
0321
0322 static struct pci_ops octeon_pci_ops = {
0323     .read   = octeon_read_config,
0324     .write  = octeon_write_config,
0325 };
0326
0327 static struct resource octeon_pci_mem_resource = {
0328     .start = 0,
0329     .end = 0,
0330     .name = "Octeon PCI MEM",
0331     .flags = IORESOURCE_MEM,
0332 };
0333
0334 /*
0335  * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
0336  * bridge
0337  */
0338 static struct resource octeon_pci_io_resource = {
0339     .start = 0x4000,
0340     .end = OCTEON_PCI_IOSPACE_SIZE - 1,
0341     .name = "Octeon PCI IO",
0342     .flags = IORESOURCE_IO,
0343 };
0344
0345 static struct pci_controller octeon_pci_controller = {
0346     .pci_ops = &octeon_pci_ops,
0347     .mem_resource = &octeon_pci_mem_resource,
0348     .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
0349     .io_resource = &octeon_pci_io_resource,
0350     .io_offset = 0,
0351     .io_map_base = OCTEON_PCI_IOSPACE_BASE,
0352 };
0353
0354
0355 /*
0356  * Low level initialize the Octeon PCI controller
0357  */
0358 static void octeon_pci_initialize(void)
0359 {
0360     union cvmx_pci_cfg01 cfg01;
0361     union cvmx_npi_ctl_status ctl_status;
0362     union cvmx_pci_ctl_status_2 ctl_status_2;
0363     union cvmx_pci_cfg19 cfg19;
0364     union cvmx_pci_cfg16 cfg16;
0365     union cvmx_pci_cfg22 cfg22;
0366     union cvmx_pci_cfg56 cfg56;
0367
0368     /* Reset the PCI Bus */
0369     cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
0370     cvmx_read_csr(CVMX_CIU_SOFT_PRST);
0371
0372     udelay(2000);       /* Hold PCI reset for 2 ms */
0373
0374     ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
0375     ctl_status.s.max_word = 1;
0376     ctl_status.s.timer = 1;
0377     cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
0378
0379     /* Deassert PCI reset and advertize PCX Host Mode Device Capability
0380        (64b) */
0381     cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
0382     cvmx_read_csr(CVMX_CIU_SOFT_PRST);
0383
0384     udelay(2000);       /* Wait 2 ms after deasserting PCI reset */
0385
0386     ctl_status_2.u32 = 0;
0387     ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0.  Must be set
0388                        before any PCI reads. */
0389     ctl_status_2.s.bar2pres = 1;    /* Enable BAR2 */
0390     ctl_status_2.s.bar2_enb = 1;
0391     ctl_status_2.s.bar2_cax = 1;    /* Don't use L2 */
0392     ctl_status_2.s.bar2_esx = 1;
0393     ctl_status_2.s.pmo_amod = 1;    /* Round robin priority */
0394     if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
0395         /* BAR1 hole */
0396         ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
0397         ctl_status_2.s.bb1_siz = 1;  /* BAR1 is 2GB */
0398         ctl_status_2.s.bb_ca = 1;    /* Don't use L2 with big bars */
0399         ctl_status_2.s.bb_es = 1;    /* Big bar in byte swap mode */
0400         ctl_status_2.s.bb1 = 1;      /* BAR1 is big */
0401         ctl_status_2.s.bb0 = 1;      /* BAR0 is big */
0402     }
0403
0404     octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
0405     udelay(2000);       /* Wait 2 ms before doing PCI reads */
0406
0407     ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
0408     pr_notice("PCI Status: %s %s-bit\n",
0409           ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
0410           ctl_status_2.s.ap_64ad ? "64" : "32");
0411
0412     if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
0413         union cvmx_pci_cnt_reg cnt_reg_start;
0414         union cvmx_pci_cnt_reg cnt_reg_end;
0415         unsigned long cycles, pci_clock;
0416
0417         cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
0418         cycles = read_c0_cvmcount();
0419         udelay(1000);
0420         cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
0421         cycles = read_c0_cvmcount() - cycles;
0422         pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
0423                 (cycles / (mips_hpt_frequency / 1000000));
0424         pr_notice("PCI Clock: %lu MHz\n", pci_clock);
0425     }
0426
0427     /*
0428      * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
0429      * in PCI-X mode to allow four outstanding splits. Otherwise,
0430      * should not change from its reset value. Don't write PCI_CFG19
0431      * in PCI mode (0x82000001 reset value), write it to 0x82000004
0432      * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
0433      * MRBCM -> must be one.
0434      */
0435     if (ctl_status_2.s.ap_pcix) {
0436         cfg19.u32 = 0;
0437         /*
0438          * Target Delayed/Split request outstanding maximum
0439          * count. [1..31] and 0=32.  NOTE: If the user
0440          * programs these bits beyond the Designed Maximum
0441          * outstanding count, then the designed maximum table
0442          * depth will be used instead.  No additional
0443          * Deferred/Split transactions will be accepted if
0444          * this outstanding maximum count is
0445          * reached. Furthermore, no additional deferred/split
0446          * transactions will be accepted if the I/O delay/ I/O
0447          * Split Request outstanding maximum is reached.
0448          */
0449         cfg19.s.tdomc = 4;
0450         /*
0451          * Master Deferred Read Request Outstanding Max Count
0452          * (PCI only).  CR4C[26:24] Max SAC cycles MAX DAC
0453          * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
0454          * 5 2 110 6 3 111 7 3 For example, if these bits are
0455          * programmed to 100, the core can support 2 DAC
0456          * cycles, 4 SAC cycles or a combination of 1 DAC and
0457          * 2 SAC cycles. NOTE: For the PCI-X maximum
0458          * outstanding split transactions, refer to
0459          * CRE0[22:20].
0460          */
0461         cfg19.s.mdrrmc = 2;
0462         /*
0463          * Master Request (Memory Read) Byte Count/Byte Enable
0464          * select. 0 = Byte Enables valid. In PCI mode, a
0465          * burst transaction cannot be performed using Memory
0466          * Read command=4?h6. 1 = DWORD Byte Count valid
0467          * (default). In PCI Mode, the memory read byte
0468          * enables are automatically generated by the
0469          * core. Note: N3 Master Request transaction sizes are
0470          * always determined through the
0471          * am_attr[<35:32>|<7:0>] field.
0472          */
0473         cfg19.s.mrbcm = 1;
0474         octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
0475     }
0476
0477
0478     cfg01.u32 = 0;
0479     cfg01.s.msae = 1;   /* Memory Space Access Enable */
0480     cfg01.s.me = 1;     /* Master Enable */
0481     cfg01.s.pee = 1;    /* PERR# Enable */
0482     cfg01.s.see = 1;    /* System Error Enable */
0483     cfg01.s.fbbe = 1;   /* Fast Back to Back Transaction Enable */
0484
0485     octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
0486
0487 #ifdef USE_OCTEON_INTERNAL_ARBITER
0488     /*
0489      * When OCTEON is a PCI host, most systems will use OCTEON's
0490      * internal arbiter, so must enable it before any PCI/PCI-X
0491      * traffic can occur.
0492      */
0493     {
0494         union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
0495
0496         pci_int_arb_cfg.u64 = 0;
0497         pci_int_arb_cfg.s.en = 1;   /* Internal arbiter enable */
0498         cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
0499     }
0500 #endif  /* USE_OCTEON_INTERNAL_ARBITER */
0501
0502     /*
0503      * Preferably written to 1 to set MLTD. [RDSATI,TRTAE,
0504      * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
0505      * 1..7.
0506      */
0507     cfg16.u32 = 0;
0508     cfg16.s.mltd = 1;   /* Master Latency Timer Disable */
0509     octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
0510
0511     /*
0512      * Should be written to 0x4ff00. MTTV -> must be zero.
0513      * FLUSH -> must be 1. MRV -> should be 0xFF.
0514      */
0515     cfg22.u32 = 0;
0516     /* Master Retry Value [1..255] and 0=infinite */
0517     cfg22.s.mrv = 0xff;
0518     /*
0519      * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
0520      * N3K operation.
0521      */
0522     cfg22.s.flush = 1;
0523     octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
0524
0525     /*
0526      * MOST Indicates the maximum number of outstanding splits (in -1
0527      * notation) when OCTEON is in PCI-X mode.  PCI-X performance is
0528      * affected by the MOST selection.  Should generally be written
0529      * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
0530      * depending on the desired MOST of 3, 2, 1, or 0, respectively.
0531      */
0532     cfg56.u32 = 0;
0533     cfg56.s.pxcid = 7;  /* RO - PCI-X Capability ID */
0534     cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */
0535     cfg56.s.dpere = 1;  /* Data Parity Error Recovery Enable */
0536     cfg56.s.roe = 1;    /* Relaxed Ordering Enable */
0537     cfg56.s.mmbc = 1;   /* Maximum Memory Byte Count
0538                    [0=512B,1=1024B,2=2048B,3=4096B] */
0539     cfg56.s.most = 3;   /* Maximum outstanding Split transactions [0=1
0540                    .. 7=32] */
0541
0542     octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
0543
0544     /*
0545      * Affects PCI performance when OCTEON services reads to its
0546      * BAR1/BAR2. Refer to Section 10.6.1.  The recommended values are
0547      * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
0548      * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
0549      * these values need to be changed so they won't possibly prefetch off
0550      * of the end of memory if PCI is DMAing a buffer at the end of
0551      * memory. Note that these values differ from their reset values.
0552      */
0553     octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
0554     octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
0555     octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
0556 }
0557
0558
0559 /*
0560  * Initialize the Octeon PCI controller
0561  */
0562 static int __init octeon_pci_setup(void)
0563 {
0564     union cvmx_npi_mem_access_subidx mem_access;
0565     int index;
0566
0567     /* Only these chips have PCI */
0568     if (octeon_has_feature(OCTEON_FEATURE_PCIE))
0569         return 0;
0570
0571     if (!octeon_is_pci_host()) {
0572         pr_notice("Not in host mode, PCI Controller not initialized\n");
0573         return 0;
0574     }
0575
0576     /* Point pcibios_map_irq() to the PCI version of it */
0577     octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
0578
0579     /* Only use the big bars on chips that support it */
0580     if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
0581         OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
0582         OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
0583         octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
0584     else
0585         octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
0586
0587     /* PCI I/O and PCI MEM values */
0588     set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
0589     ioport_resource.start = 0;
0590     ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
0591
0592     pr_notice("%s Octeon big bar support\n",
0593           (octeon_dma_bar_type ==
0594           OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
0595
0596     octeon_pci_initialize();
0597
0598     mem_access.u64 = 0;
0599     mem_access.s.esr = 1;   /* Endian-Swap on read. */
0600     mem_access.s.esw = 1;   /* Endian-Swap on write. */
0601     mem_access.s.nsr = 0;   /* No-Snoop on read. */
0602     mem_access.s.nsw = 0;   /* No-Snoop on write. */
0603     mem_access.s.ror = 0;   /* Relax Read on read. */
0604     mem_access.s.row = 0;   /* Relax Order on write. */
0605     mem_access.s.ba = 0;    /* PCI Address bits [63:36]. */
0606     cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
0607
0608     /*
0609      * Remap the Octeon BAR 2 above all 32 bit devices
0610      * (0x8000000000ul).  This is done here so it is remapped
0611      * before the readl()'s below. We don't want BAR2 overlapping
0612      * with BAR0/BAR1 during these reads.
0613      */
0614     octeon_npi_write32(CVMX_NPI_PCI_CFG08,
0615                (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
0616     octeon_npi_write32(CVMX_NPI_PCI_CFG09,
0617                (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
0618
0619     if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
0620         /* Remap the Octeon BAR 0 to 0-2GB */
0621         octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
0622         octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
0623
0624         /*
0625          * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
0626          * BAR 1 hole).
0627          */
0628         octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
0629         octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
0630
0631         /* BAR1 movable mappings set for identity mapping */
0632         octeon_bar1_pci_phys = 0x80000000ull;
0633         for (index = 0; index < 32; index++) {
0634             union cvmx_pci_bar1_indexx bar1_index;
0635
0636             bar1_index.u32 = 0;
0637             /* Address bits[35:22] sent to L2C */
0638             bar1_index.s.addr_idx =
0639                 (octeon_bar1_pci_phys >> 22) + index;
0640             /* Don't put PCI accesses in L2. */
0641             bar1_index.s.ca = 1;
0642             /* Endian Swap Mode */
0643             bar1_index.s.end_swp = 1;
0644             /* Set '1' when the selected address range is valid. */
0645             bar1_index.s.addr_v = 1;
0646             octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
0647                        bar1_index.u32);
0648         }
0649
0650         /* Devices go after BAR1 */
0651         octeon_pci_mem_resource.start =
0652             OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
0653             (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
0654         octeon_pci_mem_resource.end =
0655             octeon_pci_mem_resource.start + (1ul << 30);
0656     } else {
0657         /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
0658         octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
0659         octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
0660
0661         /* Remap the Octeon BAR 1 to map 0-128MB */
0662         octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
0663         octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
0664
0665         /* BAR1 movable regions contiguous to cover the swiotlb */
0666         octeon_bar1_pci_phys =
0667             io_tlb_default_mem.start & ~((1ull << 22) - 1);
0668
0669         for (index = 0; index < 32; index++) {
0670             union cvmx_pci_bar1_indexx bar1_index;
0671
0672             bar1_index.u32 = 0;
0673             /* Address bits[35:22] sent to L2C */
0674             bar1_index.s.addr_idx =
0675                 (octeon_bar1_pci_phys >> 22) + index;
0676             /* Don't put PCI accesses in L2. */
0677             bar1_index.s.ca = 1;
0678             /* Endian Swap Mode */
0679             bar1_index.s.end_swp = 1;
0680             /* Set '1' when the selected address range is valid. */
0681             bar1_index.s.addr_v = 1;
0682             octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
0683                        bar1_index.u32);
0684         }
0685
0686         /* Devices go after BAR0 */
0687         octeon_pci_mem_resource.start =
0688             OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
0689             (4ul << 10);
0690         octeon_pci_mem_resource.end =
0691             octeon_pci_mem_resource.start + (1ul << 30);
0692     }
0693
0694     register_pci_controller(&octeon_pci_controller);
0695
0696     /*
0697      * Clear any errors that might be pending from before the bus
0698      * was setup properly.
0699      */
0700     cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
0701
0702     if (IS_ERR(platform_device_register_simple("octeon_pci_edac",
0703                            -1, NULL, 0)))
0704         pr_err("Registration of co_pci_edac failed!\n");
0705
0706     octeon_pci_dma_init();
0707
0708     return 0;
0709 }
0710
0711 arch_initcall(octeon_pci_setup);