mips/pci/pci-mt7620.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Ralink MT7620A SoC PCI support
0004  *
0005  *  Copyright (C) 2007-2013 Bruce Chang (Mediatek)
0006  *  Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
0007  */
0008
0009 #include <linux/types.h>
0010 #include <linux/pci.h>
0011 #include <linux/io.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/of.h>
0016 #include <linux/of_irq.h>
0017 #include <linux/of_pci.h>
0018 #include <linux/reset.h>
0019 #include <linux/platform_device.h>
0020
0021 #include <asm/mach-ralink/ralink_regs.h>
0022 #include <asm/mach-ralink/mt7620.h>
0023
0024 #define RALINK_PCI_IO_MAP_BASE      0x10160000
0025 #define RALINK_PCI_MEMORY_BASE      0x0
0026
0027 #define RALINK_INT_PCIE0        4
0028
0029 #define RALINK_CLKCFG1          0x30
0030 #define RALINK_GPIOMODE         0x60
0031
0032 #define PPLL_CFG1           0x9c
0033 #define PPLL_LD             BIT(23)
0034
0035 #define PPLL_DRV            0xa0
0036 #define PDRV_SW_SET         BIT(31)
0037 #define LC_CKDRVPD          BIT(19)
0038 #define LC_CKDRVOHZ         BIT(18)
0039 #define LC_CKDRVHZ          BIT(17)
0040 #define LC_CKTEST           BIT(16)
0041
0042 /* PCI Bridge registers */
0043 #define RALINK_PCI_PCICFG_ADDR      0x00
0044 #define PCIRST              BIT(1)
0045
0046 #define RALINK_PCI_PCIENA       0x0C
0047 #define PCIINT2             BIT(20)
0048
0049 #define RALINK_PCI_CONFIG_ADDR      0x20
0050 #define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
0051 #define RALINK_PCI_MEMBASE      0x28
0052 #define RALINK_PCI_IOBASE       0x2C
0053
0054 /* PCI RC registers */
0055 #define RALINK_PCI0_BAR0SETUP_ADDR  0x10
0056 #define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
0057 #define RALINK_PCI0_ID          0x30
0058 #define RALINK_PCI0_CLASS       0x34
0059 #define RALINK_PCI0_SUBID       0x38
0060 #define RALINK_PCI0_STATUS      0x50
0061 #define PCIE_LINK_UP_ST         BIT(0)
0062
0063 #define PCIEPHY0_CFG            0x90
0064
0065 #define RALINK_PCIEPHY_P0_CTL_OFFSET    0x7498
0066 #define RALINK_PCIE0_CLK_EN     BIT(26)
0067
0068 #define BUSY                0x80000000
0069 #define WAITRETRY_MAX           10
0070 #define WRITE_MODE          (1UL << 23)
0071 #define DATA_SHIFT          0
0072 #define ADDR_SHIFT          8
0073
0074
0075 static void __iomem *bridge_base;
0076 static void __iomem *pcie_base;
0077
0078 static struct reset_control *rstpcie0;
0079
0080 static inline void bridge_w32(u32 val, unsigned reg)
0081 {
0082     iowrite32(val, bridge_base + reg);
0083 }
0084
0085 static inline u32 bridge_r32(unsigned reg)
0086 {
0087     return ioread32(bridge_base + reg);
0088 }
0089
0090 static inline void pcie_w32(u32 val, unsigned reg)
0091 {
0092     iowrite32(val, pcie_base + reg);
0093 }
0094
0095 static inline u32 pcie_r32(unsigned reg)
0096 {
0097     return ioread32(pcie_base + reg);
0098 }
0099
0100 static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
0101 {
0102     u32 val = pcie_r32(reg);
0103
0104     val &= ~clr;
0105     val |= set;
0106     pcie_w32(val, reg);
0107 }
0108
0109 static int wait_pciephy_busy(void)
0110 {
0111     unsigned long reg_value = 0x0, retry = 0;
0112
0113     while (1) {
0114         reg_value = pcie_r32(PCIEPHY0_CFG);
0115
0116         if (reg_value & BUSY)
0117             mdelay(100);
0118         else
0119             break;
0120         if (retry++ > WAITRETRY_MAX) {
0121             pr_warn("PCIE-PHY retry failed.\n");
0122             return -1;
0123         }
0124     }
0125     return 0;
0126 }
0127
0128 static void pcie_phy(unsigned long addr, unsigned long val)
0129 {
0130     wait_pciephy_busy();
0131     pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT),
0132          PCIEPHY0_CFG);
0133     mdelay(1);
0134     wait_pciephy_busy();
0135 }
0136
0137 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
0138                int size, u32 *val)
0139 {
0140     unsigned int slot = PCI_SLOT(devfn);
0141     u8 func = PCI_FUNC(devfn);
0142     u32 address;
0143     u32 data;
0144     u32 num = 0;
0145
0146     if (bus)
0147         num = bus->number;
0148
0149     address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
0150           (func << 8) | (where & 0xfc) | 0x80000000;
0151     bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
0152     data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
0153
0154     switch (size) {
0155     case 1:
0156         *val = (data >> ((where & 3) << 3)) & 0xff;
0157         break;
0158     case 2:
0159         *val = (data >> ((where & 3) << 3)) & 0xffff;
0160         break;
0161     case 4:
0162         *val = data;
0163         break;
0164     }
0165
0166     return PCIBIOS_SUCCESSFUL;
0167 }
0168
0169 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
0170                 int size, u32 val)
0171 {
0172     unsigned int slot = PCI_SLOT(devfn);
0173     u8 func = PCI_FUNC(devfn);
0174     u32 address;
0175     u32 data;
0176     u32 num = 0;
0177
0178     if (bus)
0179         num = bus->number;
0180
0181     address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
0182           (func << 8) | (where & 0xfc) | 0x80000000;
0183     bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
0184     data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
0185
0186     switch (size) {
0187     case 1:
0188         data = (data & ~(0xff << ((where & 3) << 3))) |
0189             (val << ((where & 3) << 3));
0190         break;
0191     case 2:
0192         data = (data & ~(0xffff << ((where & 3) << 3))) |
0193             (val << ((where & 3) << 3));
0194         break;
0195     case 4:
0196         data = val;
0197         break;
0198     }
0199
0200     bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
0201
0202     return PCIBIOS_SUCCESSFUL;
0203 }
0204
0205 struct pci_ops mt7620_pci_ops = {
0206     .read   = pci_config_read,
0207     .write  = pci_config_write,
0208 };
0209
0210 static struct resource mt7620_res_pci_mem1;
0211 static struct resource mt7620_res_pci_io1;
0212 struct pci_controller mt7620_controller = {
0213     .pci_ops    = &mt7620_pci_ops,
0214     .mem_resource   = &mt7620_res_pci_mem1,
0215     .mem_offset = 0x00000000UL,
0216     .io_resource    = &mt7620_res_pci_io1,
0217     .io_offset  = 0x00000000UL,
0218     .io_map_base    = 0xa0000000,
0219 };
0220
0221 static int mt7620_pci_hw_init(struct platform_device *pdev)
0222 {
0223     /* bypass PCIe DLL */
0224     pcie_phy(0x0, 0x80);
0225     pcie_phy(0x1, 0x04);
0226
0227     /* Elastic buffer control */
0228     pcie_phy(0x68, 0xB4);
0229
0230     /* put core into reset */
0231     pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
0232     reset_control_assert(rstpcie0);
0233
0234     /* disable power and all clocks */
0235     rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
0236     rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
0237
0238     /* bring core out of reset */
0239     reset_control_deassert(rstpcie0);
0240     rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
0241     mdelay(100);
0242
0243     if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
0244         dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");
0245         reset_control_assert(rstpcie0);
0246         rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
0247         return -1;
0248     }
0249
0250     /* power up the bus */
0251     rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
0252             PPLL_DRV);
0253
0254     return 0;
0255 }
0256
0257 static int mt7628_pci_hw_init(struct platform_device *pdev)
0258 {
0259     u32 val = 0;
0260
0261     /* bring the core out of reset */
0262     rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
0263     reset_control_deassert(rstpcie0);
0264
0265     /* enable the pci clk */
0266     rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
0267     mdelay(100);
0268
0269     /* voodoo from the SDK driver */
0270     pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
0271
0272     pci_config_read(NULL, 0, 0x70c, 4, &val);
0273     val &= ~(0xff) << 8;
0274     val |= 0x50 << 8;
0275     pci_config_write(NULL, 0, 0x70c, 4, val);
0276
0277     pci_config_read(NULL, 0, 0x70c, 4, &val);
0278     dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
0279
0280     return 0;
0281 }
0282
0283 static int mt7620_pci_probe(struct platform_device *pdev)
0284 {
0285     struct resource *bridge_res = platform_get_resource(pdev,
0286                                 IORESOURCE_MEM, 0);
0287     struct resource *pcie_res = platform_get_resource(pdev,
0288                               IORESOURCE_MEM, 1);
0289     u32 val = 0;
0290
0291     rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
0292     if (IS_ERR(rstpcie0))
0293         return PTR_ERR(rstpcie0);
0294
0295     bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
0296     if (IS_ERR(bridge_base))
0297         return PTR_ERR(bridge_base);
0298
0299     pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
0300     if (IS_ERR(pcie_base))
0301         return PTR_ERR(pcie_base);
0302
0303     iomem_resource.start = 0;
0304     iomem_resource.end = ~0;
0305     ioport_resource.start = 0;
0306     ioport_resource.end = ~0;
0307
0308     /* bring up the pci core */
0309     switch (ralink_soc) {
0310     case MT762X_SOC_MT7620A:
0311         if (mt7620_pci_hw_init(pdev))
0312             return -1;
0313         break;
0314
0315     case MT762X_SOC_MT7628AN:
0316     case MT762X_SOC_MT7688:
0317         if (mt7628_pci_hw_init(pdev))
0318             return -1;
0319         break;
0320
0321     default:
0322         dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
0323         return -1;
0324     }
0325     mdelay(50);
0326
0327     /* enable write access */
0328     pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
0329     mdelay(100);
0330
0331     /* check if there is a card present */
0332     if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
0333         reset_control_assert(rstpcie0);
0334         rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
0335         if (ralink_soc == MT762X_SOC_MT7620A)
0336             rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
0337         dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
0338         return -1;
0339     }
0340
0341     /* setup ranges */
0342     bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
0343     bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
0344
0345     pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
0346     pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
0347     pcie_w32(0x06040001, RALINK_PCI0_CLASS);
0348
0349     /* enable interrupts */
0350     pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
0351
0352     /* voodoo from the SDK driver */
0353     pci_config_read(NULL, 0, 4, 4, &val);
0354     pci_config_write(NULL, 0, 4, 4, val | 0x7);
0355
0356     pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
0357     register_pci_controller(&mt7620_controller);
0358
0359     return 0;
0360 }
0361
0362 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0363 {
0364     u16 cmd;
0365     u32 val;
0366     int irq = 0;
0367
0368     if ((dev->bus->number == 0) && (slot == 0)) {
0369         pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
0370         pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
0371                  RALINK_PCI_MEMORY_BASE);
0372         pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
0373     } else if ((dev->bus->number == 1) && (slot == 0x0)) {
0374         irq = RALINK_INT_PCIE0;
0375     } else {
0376         dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
0377             dev->bus->number, slot);
0378         return 0;
0379     }
0380     dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
0381         dev->bus->number, slot, irq);
0382
0383     /* configure the cache line size to 0x14 */
0384     pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
0385
0386     /* configure latency timer to 0xff */
0387     pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
0388     pci_read_config_word(dev, PCI_COMMAND, &cmd);
0389
0390     /* setup the slot */
0391     cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
0392     pci_write_config_word(dev, PCI_COMMAND, cmd);
0393     pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
0394
0395     return irq;
0396 }
0397
0398 int pcibios_plat_dev_init(struct pci_dev *dev)
0399 {
0400     return 0;
0401 }
0402
0403 static const struct of_device_id mt7620_pci_ids[] = {
0404     { .compatible = "mediatek,mt7620-pci" },
0405     {},
0406 };
0407
0408 static struct platform_driver mt7620_pci_driver = {
0409     .probe = mt7620_pci_probe,
0410     .driver = {
0411         .name = "mt7620-pci",
0412         .of_match_table = of_match_ptr(mt7620_pci_ids),
0413     },
0414 };
0415
0416 static int __init mt7620_pci_init(void)
0417 {
0418     return platform_driver_register(&mt7620_pci_driver);
0419 }
0420
0421 arch_initcall(mt7620_pci_init);