mips/pci/pci-malta.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
0004  *  All rights reserved.
0005  *  Authors: Carsten Langgaard <carstenl@mips.com>
0006  *       Maciej W. Rozycki <macro@mips.com>
0007  *
0008  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
0009  *
0010  * MIPS boards specific PCI support.
0011  */
0012 #include <linux/types.h>
0013 #include <linux/pci.h>
0014 #include <linux/kernel.h>
0015 #include <linux/init.h>
0016
0017 #include <asm/gt64120.h>
0018 #include <asm/mips-cps.h>
0019 #include <asm/mips-boards/generic.h>
0020 #include <asm/mips-boards/bonito64.h>
0021 #include <asm/mips-boards/msc01_pci.h>
0022
0023 static struct resource bonito64_mem_resource = {
0024     .name   = "Bonito PCI MEM",
0025     .flags  = IORESOURCE_MEM,
0026 };
0027
0028 static struct resource bonito64_io_resource = {
0029     .name   = "Bonito PCI I/O",
0030     .start  = 0x00000000UL,
0031     .end    = 0x000fffffUL,
0032     .flags  = IORESOURCE_IO,
0033 };
0034
0035 static struct resource gt64120_mem_resource = {
0036     .name   = "GT-64120 PCI MEM",
0037     .flags  = IORESOURCE_MEM,
0038 };
0039
0040 static struct resource gt64120_io_resource = {
0041     .name   = "GT-64120 PCI I/O",
0042     .flags  = IORESOURCE_IO,
0043 };
0044
0045 static struct resource msc_mem_resource = {
0046     .name   = "MSC PCI MEM",
0047     .flags  = IORESOURCE_MEM,
0048 };
0049
0050 static struct resource msc_io_resource = {
0051     .name   = "MSC PCI I/O",
0052     .flags  = IORESOURCE_IO,
0053 };
0054
0055 extern struct pci_ops bonito64_pci_ops;
0056 extern struct pci_ops gt64xxx_pci0_ops;
0057 extern struct pci_ops msc_pci_ops;
0058
0059 static struct pci_controller bonito64_controller = {
0060     .pci_ops    = &bonito64_pci_ops,
0061     .io_resource    = &bonito64_io_resource,
0062     .mem_resource   = &bonito64_mem_resource,
0063     .io_offset  = 0x00000000UL,
0064 };
0065
0066 static struct pci_controller gt64120_controller = {
0067     .pci_ops    = &gt64xxx_pci0_ops,
0068     .io_resource    = &gt64120_io_resource,
0069     .mem_resource   = &gt64120_mem_resource,
0070 };
0071
0072 static struct pci_controller msc_controller = {
0073     .pci_ops    = &msc_pci_ops,
0074     .io_resource    = &msc_io_resource,
0075     .mem_resource   = &msc_mem_resource,
0076 };
0077
0078 void __init mips_pcibios_init(void)
0079 {
0080     struct pci_controller *controller;
0081     resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;
0082
0083     switch (mips_revision_sconid) {
0084     case MIPS_REVISION_SCON_GT64120:
0085         /*
0086          * Due to a bug in the Galileo system controller, we need
0087          * to setup the PCI BAR for the Galileo internal registers.
0088          * This should be done in the bios/bootprom and will be
0089          * fixed in a later revision of YAMON (the MIPS boards
0090          * boot prom).
0091          */
0092         GT_WRITE(GT_PCI0_CFGADDR_OFS,
0093              (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
0094              (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
0095              (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
0096              ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
0097              GT_PCI0_CFGADDR_CONFIGEN_BIT);
0098
0099         /* Perform the write */
0100         GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
0101
0102         /* Set up resource ranges from the controller's registers.  */
0103         start = GT_READ(GT_PCI0M0LD_OFS);
0104         end = GT_READ(GT_PCI0M0HD_OFS);
0105         map = GT_READ(GT_PCI0M0REMAP_OFS);
0106         end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
0107         start1 = GT_READ(GT_PCI0M1LD_OFS);
0108         end1 = GT_READ(GT_PCI0M1HD_OFS);
0109         map1 = GT_READ(GT_PCI0M1REMAP_OFS);
0110         end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
0111         /* Cannot support multiple windows, use the wider.  */
0112         if (end1 - start1 > end - start) {
0113             start = start1;
0114             end = end1;
0115             map = map1;
0116         }
0117         mask = ~(start ^ end);
0118         /* We don't support remapping with a discontiguous mask.  */
0119         BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
0120                mask != ~((mask & -mask) - 1));
0121         gt64120_mem_resource.start = start;
0122         gt64120_mem_resource.end = end;
0123         gt64120_controller.mem_offset = (start & mask) - (map & mask);
0124         /* Addresses are 36-bit, so do shifts in the destinations.  */
0125         gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
0126         gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
0127         gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
0128         gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
0129
0130         start = GT_READ(GT_PCI0IOLD_OFS);
0131         end = GT_READ(GT_PCI0IOHD_OFS);
0132         map = GT_READ(GT_PCI0IOREMAP_OFS);
0133         end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
0134         mask = ~(start ^ end);
0135         /* We don't support remapping with a discontiguous mask.  */
0136         BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
0137                mask != ~((mask & -mask) - 1));
0138         gt64120_io_resource.start = map & mask;
0139         gt64120_io_resource.end = (map & mask) | ~mask;
0140         gt64120_controller.io_offset = 0;
0141         /* Addresses are 36-bit, so do shifts in the destinations.  */
0142         gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
0143         gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
0144         gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
0145
0146         controller = &gt64120_controller;
0147         break;
0148
0149     case MIPS_REVISION_SCON_BONITO:
0150         /* Set up resource ranges from the controller's registers.  */
0151         map = BONITO_PCIMAP;
0152         map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
0153                BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
0154         map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
0155                BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
0156         map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
0157                BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
0158         /* Combine as many adjacent windows as possible.  */
0159         map = map1;
0160         start = BONITO_PCILO0_BASE;
0161         end = 1;
0162         if (map3 == map2 + 1) {
0163             map = map2;
0164             start = BONITO_PCILO1_BASE;
0165             end++;
0166         }
0167         if (map2 == map1 + 1) {
0168             map = map1;
0169             start = BONITO_PCILO0_BASE;
0170             end++;
0171         }
0172         bonito64_mem_resource.start = start;
0173         bonito64_mem_resource.end = start +
0174                         BONITO_PCIMAP_WINBASE(end) - 1;
0175         bonito64_controller.mem_offset = start -
0176                          BONITO_PCIMAP_WINBASE(map);
0177
0178         controller = &bonito64_controller;
0179         break;
0180
0181     case MIPS_REVISION_SCON_SOCIT:
0182     case MIPS_REVISION_SCON_ROCIT:
0183     case MIPS_REVISION_SCON_SOCITSC:
0184     case MIPS_REVISION_SCON_SOCITSCP:
0185         /* Set up resource ranges from the controller's registers.  */
0186         MSC_READ(MSC01_PCI_SC2PMBASL, start);
0187         MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
0188         MSC_READ(MSC01_PCI_SC2PMMAPL, map);
0189         msc_mem_resource.start = start & mask;
0190         msc_mem_resource.end = (start & mask) | ~mask;
0191         msc_controller.mem_offset = (start & mask) - (map & mask);
0192         if (mips_cps_numiocu(0)) {
0193             write_gcr_reg0_base(start);
0194             write_gcr_reg0_mask(mask |
0195                         CM_GCR_REGn_MASK_CMTGT_IOCU0);
0196         }
0197         MSC_READ(MSC01_PCI_SC2PIOBASL, start);
0198         MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
0199         MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
0200         msc_io_resource.start = map & mask;
0201         msc_io_resource.end = (map & mask) | ~mask;
0202         msc_controller.io_offset = 0;
0203         ioport_resource.end = ~mask;
0204         if (mips_cps_numiocu(0)) {
0205             write_gcr_reg1_base(start);
0206             write_gcr_reg1_mask(mask |
0207                         CM_GCR_REGn_MASK_CMTGT_IOCU0);
0208         }
0209         /* If ranges overlap I/O takes precedence.  */
0210         start = start & mask;
0211         end = start | ~mask;
0212         if ((start >= msc_mem_resource.start &&
0213              start <= msc_mem_resource.end) ||
0214             (end >= msc_mem_resource.start &&
0215              end <= msc_mem_resource.end)) {
0216             /* Use the larger space.  */
0217             start = max(start, msc_mem_resource.start);
0218             end = min(end, msc_mem_resource.end);
0219             if (start - msc_mem_resource.start >=
0220                 msc_mem_resource.end - end)
0221                 msc_mem_resource.end = start - 1;
0222             else
0223                 msc_mem_resource.start = end + 1;
0224         }
0225
0226         controller = &msc_controller;
0227         break;
0228     default:
0229         return;
0230     }
0231
0232     /* PIIX4 ACPI starts at 0x1000 */
0233     if (controller->io_resource->start < 0x00001000UL)
0234         controller->io_resource->start = 0x00001000UL;
0235
0236     iomem_resource.end &= 0xfffffffffULL;           /* 64 GB */
0237     ioport_resource.end = controller->io_resource->end;
0238
0239     controller->io_map_base = mips_io_port_base;
0240
0241     register_pci_controller(controller);
0242 }