mips/pci/pci-legacy.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *
0004  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
0005  * Copyright (C) 2011 Wind River Systems,
0006  *   written by Ralf Baechle (ralf@linux-mips.org)
0007  */
0008 #include <linux/bug.h>
0009 #include <linux/kernel.h>
0010 #include <linux/mm.h>
0011 #include <linux/memblock.h>
0012 #include <linux/export.h>
0013 #include <linux/init.h>
0014 #include <linux/types.h>
0015 #include <linux/pci.h>
0016 #include <linux/of_address.h>
0017
0018 #include <asm/cpu-info.h>
0019
0020 /*
0021  * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
0022  * assignments.
0023  */
0024
0025 /*
0026  * The PCI controller list.
0027  */
0028 static LIST_HEAD(controllers);
0029
0030 static int pci_initialized;
0031
0032 /*
0033  * We need to avoid collisions with `mirrored' VGA ports
0034  * and other strange ISA hardware, so we always want the
0035  * addresses to be allocated in the 0x000-0x0ff region
0036  * modulo 0x400.
0037  *
0038  * Why? Because some silly external IO cards only decode
0039  * the low 10 bits of the IO address. The 0x00-0xff region
0040  * is reserved for motherboard devices that decode all 16
0041  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
0042  * but we want to try to avoid allocating at 0x2900-0x2bff
0043  * which might have be mirrored at 0x0100-0x03ff..
0044  */
0045 resource_size_t
0046 pcibios_align_resource(void *data, const struct resource *res,
0047                resource_size_t size, resource_size_t align)
0048 {
0049     struct pci_dev *dev = data;
0050     struct pci_controller *hose = dev->sysdata;
0051     resource_size_t start = res->start;
0052
0053     if (res->flags & IORESOURCE_IO) {
0054         /* Make sure we start at our min on all hoses */
0055         if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
0056             start = PCIBIOS_MIN_IO + hose->io_resource->start;
0057
0058         /*
0059          * Put everything into 0x00-0xff region modulo 0x400
0060          */
0061         if (start & 0x300)
0062             start = (start + 0x3ff) & ~0x3ff;
0063     } else if (res->flags & IORESOURCE_MEM) {
0064         /* Make sure we start at our min on all hoses */
0065         if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
0066             start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
0067     }
0068
0069     return start;
0070 }
0071
0072 static void pcibios_scanbus(struct pci_controller *hose)
0073 {
0074     static int next_busno;
0075     static int need_domain_info;
0076     LIST_HEAD(resources);
0077     struct pci_bus *bus;
0078     struct pci_host_bridge *bridge;
0079     int ret;
0080
0081     bridge = pci_alloc_host_bridge(0);
0082     if (!bridge)
0083         return;
0084
0085     if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
0086         next_busno = (*hose->get_busno)();
0087
0088     pci_add_resource_offset(&resources,
0089                 hose->mem_resource, hose->mem_offset);
0090     pci_add_resource_offset(&resources,
0091                 hose->io_resource, hose->io_offset);
0092     list_splice_init(&resources, &bridge->windows);
0093     bridge->dev.parent = NULL;
0094     bridge->sysdata = hose;
0095     bridge->busnr = next_busno;
0096     bridge->ops = hose->pci_ops;
0097     bridge->swizzle_irq = pci_common_swizzle;
0098     bridge->map_irq = pcibios_map_irq;
0099     ret = pci_scan_root_bus_bridge(bridge);
0100     if (ret) {
0101         pci_free_host_bridge(bridge);
0102         return;
0103     }
0104
0105     hose->bus = bus = bridge->bus;
0106
0107     need_domain_info = need_domain_info || pci_domain_nr(bus);
0108     set_pci_need_domain_info(hose, need_domain_info);
0109
0110     next_busno = bus->busn_res.end + 1;
0111     /* Don't allow 8-bit bus number overflow inside the hose -
0112        reserve some space for bridges. */
0113     if (next_busno > 224) {
0114         next_busno = 0;
0115         need_domain_info = 1;
0116     }
0117
0118     /*
0119      * We insert PCI resources into the iomem_resource and
0120      * ioport_resource trees in either pci_bus_claim_resources()
0121      * or pci_bus_assign_resources().
0122      */
0123     if (pci_has_flag(PCI_PROBE_ONLY)) {
0124         pci_bus_claim_resources(bus);
0125     } else {
0126         struct pci_bus *child;
0127
0128         pci_bus_size_bridges(bus);
0129         pci_bus_assign_resources(bus);
0130         list_for_each_entry(child, &bus->children, node)
0131             pcie_bus_configure_settings(child);
0132     }
0133     pci_bus_add_devices(bus);
0134 }
0135
0136 #ifdef CONFIG_OF
0137 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
0138 {
0139     struct of_pci_range range;
0140     struct of_pci_range_parser parser;
0141
0142     hose->of_node = node;
0143
0144     if (of_pci_range_parser_init(&parser, node))
0145         return;
0146
0147     for_each_of_pci_range(&parser, &range) {
0148         struct resource *res = NULL;
0149
0150         switch (range.flags & IORESOURCE_TYPE_BITS) {
0151         case IORESOURCE_IO:
0152             hose->io_map_base =
0153                 (unsigned long)ioremap(range.cpu_addr,
0154                                range.size);
0155             res = hose->io_resource;
0156             break;
0157         case IORESOURCE_MEM:
0158             res = hose->mem_resource;
0159             break;
0160         }
0161         if (res != NULL) {
0162             res->name = node->full_name;
0163             res->flags = range.flags;
0164             res->start = range.cpu_addr;
0165             res->end = range.cpu_addr + range.size - 1;
0166             res->parent = res->child = res->sibling = NULL;
0167         }
0168     }
0169 }
0170
0171 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
0172 {
0173     struct pci_controller *hose = bus->sysdata;
0174
0175     return of_node_get(hose->of_node);
0176 }
0177 #endif
0178
0179 static DEFINE_MUTEX(pci_scan_mutex);
0180
0181 void register_pci_controller(struct pci_controller *hose)
0182 {
0183     struct resource *parent;
0184
0185     parent = hose->mem_resource->parent;
0186     if (!parent)
0187         parent = &iomem_resource;
0188
0189     if (request_resource(parent, hose->mem_resource) < 0)
0190         goto out;
0191
0192     parent = hose->io_resource->parent;
0193     if (!parent)
0194         parent = &ioport_resource;
0195
0196     if (request_resource(parent, hose->io_resource) < 0) {
0197         release_resource(hose->mem_resource);
0198         goto out;
0199     }
0200
0201     INIT_LIST_HEAD(&hose->list);
0202     list_add_tail(&hose->list, &controllers);
0203
0204     /*
0205      * Do not panic here but later - this might happen before console init.
0206      */
0207     if (!hose->io_map_base) {
0208         printk(KERN_WARNING
0209                "registering PCI controller with io_map_base unset\n");
0210     }
0211
0212     /*
0213      * Scan the bus if it is register after the PCI subsystem
0214      * initialization.
0215      */
0216     if (pci_initialized) {
0217         mutex_lock(&pci_scan_mutex);
0218         pcibios_scanbus(hose);
0219         mutex_unlock(&pci_scan_mutex);
0220     }
0221
0222     return;
0223
0224 out:
0225     printk(KERN_WARNING
0226            "Skipping PCI bus scan due to resource conflict\n");
0227 }
0228
0229 static int __init pcibios_init(void)
0230 {
0231     struct pci_controller *hose;
0232
0233     /* Scan all of the recorded PCI controllers.  */
0234     list_for_each_entry(hose, &controllers, list)
0235         pcibios_scanbus(hose);
0236
0237     pci_initialized = 1;
0238
0239     return 0;
0240 }
0241
0242 subsys_initcall(pcibios_init);
0243
0244 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
0245 {
0246     u16 cmd, old_cmd;
0247     int idx;
0248     struct resource *r;
0249
0250     pci_read_config_word(dev, PCI_COMMAND, &cmd);
0251     old_cmd = cmd;
0252     for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
0253         /* Only set up the requested stuff */
0254         if (!(mask & (1<<idx)))
0255             continue;
0256
0257         r = &dev->resource[idx];
0258         if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
0259             continue;
0260         if ((idx == PCI_ROM_RESOURCE) &&
0261                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
0262             continue;
0263         if (!r->start && r->end) {
0264             pci_err(dev,
0265                 "can't enable device: resource collisions\n");
0266             return -EINVAL;
0267         }
0268         if (r->flags & IORESOURCE_IO)
0269             cmd |= PCI_COMMAND_IO;
0270         if (r->flags & IORESOURCE_MEM)
0271             cmd |= PCI_COMMAND_MEMORY;
0272     }
0273     if (cmd != old_cmd) {
0274         pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
0275         pci_write_config_word(dev, PCI_COMMAND, cmd);
0276     }
0277     return 0;
0278 }
0279
0280 int pcibios_enable_device(struct pci_dev *dev, int mask)
0281 {
0282     int err = pcibios_enable_resources(dev, mask);
0283
0284     if (err < 0)
0285         return err;
0286
0287     return pcibios_plat_dev_init(dev);
0288 }
0289
0290 void pcibios_fixup_bus(struct pci_bus *bus)
0291 {
0292     struct pci_dev *dev = bus->self;
0293
0294     if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
0295         (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
0296         pci_read_bridge_bases(bus);
0297     }
0298 }
0299
0300 char * (*pcibios_plat_setup)(char *str) __initdata;
0301
0302 char *__init pcibios_setup(char *str)
0303 {
0304     if (pcibios_plat_setup)
0305         return pcibios_plat_setup(str);
0306     return str;
0307 }