mips/pci/pci-lantiq.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
0005  */
0006
0007 #include <linux/types.h>
0008 #include <linux/pci.h>
0009 #include <linux/kernel.h>
0010 #include <linux/init.h>
0011 #include <linux/delay.h>
0012 #include <linux/mm.h>
0013 #include <linux/vmalloc.h>
0014 #include <linux/clk.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/of_gpio.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/of_pci.h>
0019
0020 #include <asm/addrspace.h>
0021
0022 #include <lantiq_soc.h>
0023 #include <lantiq_irq.h>
0024
0025 #include "pci-lantiq.h"
0026
0027 #define PCI_CR_FCI_ADDR_MAP0        0x00C0
0028 #define PCI_CR_FCI_ADDR_MAP1        0x00C4
0029 #define PCI_CR_FCI_ADDR_MAP2        0x00C8
0030 #define PCI_CR_FCI_ADDR_MAP3        0x00CC
0031 #define PCI_CR_FCI_ADDR_MAP4        0x00D0
0032 #define PCI_CR_FCI_ADDR_MAP5        0x00D4
0033 #define PCI_CR_FCI_ADDR_MAP6        0x00D8
0034 #define PCI_CR_FCI_ADDR_MAP7        0x00DC
0035 #define PCI_CR_CLK_CTRL         0x0000
0036 #define PCI_CR_PCI_MOD          0x0030
0037 #define PCI_CR_PC_ARB           0x0080
0038 #define PCI_CR_FCI_ADDR_MAP11hg     0x00E4
0039 #define PCI_CR_BAR11MASK        0x0044
0040 #define PCI_CR_BAR12MASK        0x0048
0041 #define PCI_CR_BAR13MASK        0x004C
0042 #define PCI_CS_BASE_ADDR1       0x0010
0043 #define PCI_CR_PCI_ADDR_MAP11       0x0064
0044 #define PCI_CR_FCI_BURST_LENGTH     0x00E8
0045 #define PCI_CR_PCI_EOI          0x002C
0046 #define PCI_CS_STS_CMD          0x0004
0047
0048 #define PCI_MASTER0_REQ_MASK_2BITS  8
0049 #define PCI_MASTER1_REQ_MASK_2BITS  10
0050 #define PCI_MASTER2_REQ_MASK_2BITS  12
0051 #define INTERNAL_ARB_ENABLE_BIT     0
0052
0053 #define LTQ_CGU_IFCCR       0x0018
0054 #define LTQ_CGU_PCICR       0x0034
0055
0056 #define ltq_pci_w32(x, y)   ltq_w32((x), ltq_pci_membase + (y))
0057 #define ltq_pci_r32(x)      ltq_r32(ltq_pci_membase + (x))
0058
0059 #define ltq_pci_cfg_w32(x, y)   ltq_w32((x), ltq_pci_mapped_cfg + (y))
0060 #define ltq_pci_cfg_r32(x)  ltq_r32(ltq_pci_mapped_cfg + (x))
0061
0062 __iomem void *ltq_pci_mapped_cfg;
0063 static __iomem void *ltq_pci_membase;
0064
0065 static int reset_gpio;
0066 static struct clk *clk_pci, *clk_external;
0067 static struct resource pci_io_resource;
0068 static struct resource pci_mem_resource;
0069 static struct pci_ops pci_ops = {
0070     .read   = ltq_pci_read_config_dword,
0071     .write  = ltq_pci_write_config_dword
0072 };
0073
0074 static struct pci_controller pci_controller = {
0075     .pci_ops    = &pci_ops,
0076     .mem_resource   = &pci_mem_resource,
0077     .mem_offset = 0x00000000UL,
0078     .io_resource    = &pci_io_resource,
0079     .io_offset  = 0x00000000UL,
0080 };
0081
0082 static inline u32 ltq_calc_bar11mask(void)
0083 {
0084     u32 mem, bar11mask;
0085
0086     /* BAR11MASK value depends on available memory on system. */
0087     mem = get_num_physpages() * PAGE_SIZE;
0088     bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
0089
0090     return bar11mask;
0091 }
0092
0093 static int ltq_pci_startup(struct platform_device *pdev)
0094 {
0095     struct device_node *node = pdev->dev.of_node;
0096     const __be32 *req_mask, *bus_clk;
0097     u32 temp_buffer;
0098
0099     /* get our clocks */
0100     clk_pci = clk_get(&pdev->dev, NULL);
0101     if (IS_ERR(clk_pci)) {
0102         dev_err(&pdev->dev, "failed to get pci clock\n");
0103         return PTR_ERR(clk_pci);
0104     }
0105
0106     clk_external = clk_get(&pdev->dev, "external");
0107     if (IS_ERR(clk_external)) {
0108         clk_put(clk_pci);
0109         dev_err(&pdev->dev, "failed to get external pci clock\n");
0110         return PTR_ERR(clk_external);
0111     }
0112
0113     /* read the bus speed that we want */
0114     bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
0115     if (bus_clk)
0116         clk_set_rate(clk_pci, *bus_clk);
0117
0118     /* and enable the clocks */
0119     clk_enable(clk_pci);
0120     if (of_find_property(node, "lantiq,external-clock", NULL))
0121         clk_enable(clk_external);
0122     else
0123         clk_disable(clk_external);
0124
0125     /* setup reset gpio used by pci */
0126     reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
0127     if (gpio_is_valid(reset_gpio)) {
0128         int ret = devm_gpio_request(&pdev->dev,
0129                         reset_gpio, "pci-reset");
0130         if (ret) {
0131             dev_err(&pdev->dev,
0132                 "failed to request gpio %d\n", reset_gpio);
0133             return ret;
0134         }
0135         gpio_direction_output(reset_gpio, 1);
0136     }
0137
0138     /* enable auto-switching between PCI and EBU */
0139     ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
0140
0141     /* busy, i.e. configuration is not done, PCI access has to be retried */
0142     ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
0143     wmb();
0144     /* BUS Master/IO/MEM access */
0145     ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
0146
0147     /* enable external 2 PCI masters */
0148     temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
0149     /* setup the request mask */
0150     req_mask = of_get_property(node, "req-mask", NULL);
0151     if (req_mask)
0152         temp_buffer &= ~((*req_mask & 0xf) << 16);
0153     else
0154         temp_buffer &= ~0xf0000;
0155     /* enable internal arbiter */
0156     temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
0157     /* enable internal PCI master reqest */
0158     temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
0159
0160     /* enable EBU request */
0161     temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
0162
0163     /* enable all external masters request */
0164     temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
0165     ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
0166     wmb();
0167
0168     /* setup BAR memory regions */
0169     ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
0170     ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
0171     ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
0172     ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
0173     ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
0174     ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
0175     ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
0176     ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
0177     ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
0178     ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
0179     ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
0180     ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
0181     /* both TX and RX endian swap are enabled */
0182     ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
0183     wmb();
0184     ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
0185         PCI_CR_BAR12MASK);
0186     ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
0187         PCI_CR_BAR13MASK);
0188     /*use 8 dw burst length */
0189     ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
0190     ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
0191     wmb();
0192
0193     /* setup irq line */
0194     ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
0195     ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
0196
0197     /* toggle reset pin */
0198     if (gpio_is_valid(reset_gpio)) {
0199         __gpio_set_value(reset_gpio, 0);
0200         wmb();
0201         mdelay(1);
0202         __gpio_set_value(reset_gpio, 1);
0203     }
0204     return 0;
0205 }
0206
0207 static int ltq_pci_probe(struct platform_device *pdev)
0208 {
0209     struct resource *res_cfg, *res_bridge;
0210
0211     pci_clear_flags(PCI_PROBE_ONLY);
0212
0213     res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0214     ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
0215     if (IS_ERR(ltq_pci_membase))
0216         return PTR_ERR(ltq_pci_membase);
0217
0218     res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0219     ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
0220     if (IS_ERR(ltq_pci_mapped_cfg))
0221         return PTR_ERR(ltq_pci_mapped_cfg);
0222
0223     ltq_pci_startup(pdev);
0224
0225     pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
0226     register_pci_controller(&pci_controller);
0227     return 0;
0228 }
0229
0230 static const struct of_device_id ltq_pci_match[] = {
0231     { .compatible = "lantiq,pci-xway" },
0232     {},
0233 };
0234
0235 static struct platform_driver ltq_pci_driver = {
0236     .probe = ltq_pci_probe,
0237     .driver = {
0238         .name = "pci-xway",
0239         .of_match_table = ltq_pci_match,
0240     },
0241 };
0242
0243 int __init pcibios_init(void)
0244 {
0245     int ret = platform_driver_register(&ltq_pci_driver);
0246     if (ret)
0247         pr_info("pci-xway: Error registering platform driver!");
0248     return ret;
0249 }
0250
0251 arch_initcall(pcibios_init);