mips/pci/pci-ip32.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2000, 2001 Keith M Wesolowski
0007  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
0008  */
0009 #include <linux/kernel.h>
0010 #include <linux/init.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/pci.h>
0013 #include <linux/types.h>
0014 #include <asm/ip32/mace.h>
0015 #include <asm/ip32/ip32_ints.h>
0016
0017 #undef DEBUG_MACE_PCI
0018
0019 /*
0020  * Handle errors from the bridge.  This includes master and target aborts,
0021  * various command and address errors, and the interrupt test.  This gets
0022  * registered on the bridge error irq.  It's conceivable that some of these
0023  * conditions warrant a panic.  Anybody care to say which ones?
0024  */
0025 static irqreturn_t macepci_error(int irq, void *dev)
0026 {
0027     char s;
0028     unsigned int flags = mace->pci.error;
0029     unsigned int addr = mace->pci.error_addr;
0030
0031     if (flags & MACEPCI_ERROR_MEMORY_ADDR)
0032         s = 'M';
0033     else if (flags & MACEPCI_ERROR_CONFIG_ADDR)
0034         s = 'C';
0035     else
0036         s = 'X';
0037
0038     if (flags & MACEPCI_ERROR_MASTER_ABORT) {
0039         printk("MACEPCI: Master abort at 0x%08x (%c)\n", addr, s);
0040         flags &= ~MACEPCI_ERROR_MASTER_ABORT;
0041     }
0042     if (flags & MACEPCI_ERROR_TARGET_ABORT) {
0043         printk("MACEPCI: Target abort at 0x%08x (%c)\n", addr, s);
0044         flags &= ~MACEPCI_ERROR_TARGET_ABORT;
0045     }
0046     if (flags & MACEPCI_ERROR_DATA_PARITY_ERR) {
0047         printk("MACEPCI: Data parity error at 0x%08x (%c)\n", addr, s);
0048         flags &= ~MACEPCI_ERROR_DATA_PARITY_ERR;
0049     }
0050     if (flags & MACEPCI_ERROR_RETRY_ERR) {
0051         printk("MACEPCI: Retry error at 0x%08x (%c)\n", addr, s);
0052         flags &= ~MACEPCI_ERROR_RETRY_ERR;
0053     }
0054     if (flags & MACEPCI_ERROR_ILLEGAL_CMD) {
0055         printk("MACEPCI: Illegal command at 0x%08x (%c)\n", addr, s);
0056         flags &= ~MACEPCI_ERROR_ILLEGAL_CMD;
0057     }
0058     if (flags & MACEPCI_ERROR_SYSTEM_ERR) {
0059         printk("MACEPCI: System error at 0x%08x (%c)\n", addr, s);
0060         flags &= ~MACEPCI_ERROR_SYSTEM_ERR;
0061     }
0062     if (flags & MACEPCI_ERROR_PARITY_ERR) {
0063         printk("MACEPCI: Parity error at 0x%08x (%c)\n", addr, s);
0064         flags &= ~MACEPCI_ERROR_PARITY_ERR;
0065     }
0066     if (flags & MACEPCI_ERROR_OVERRUN) {
0067         printk("MACEPCI: Overrun error at 0x%08x (%c)\n", addr, s);
0068         flags &= ~MACEPCI_ERROR_OVERRUN;
0069     }
0070     if (flags & MACEPCI_ERROR_SIG_TABORT) {
0071         printk("MACEPCI: Signaled target abort (clearing)\n");
0072         flags &= ~MACEPCI_ERROR_SIG_TABORT;
0073     }
0074     if (flags & MACEPCI_ERROR_INTERRUPT_TEST) {
0075         printk("MACEPCI: Interrupt test triggered (clearing)\n");
0076         flags &= ~MACEPCI_ERROR_INTERRUPT_TEST;
0077     }
0078
0079     mace->pci.error = flags;
0080
0081     return IRQ_HANDLED;
0082 }
0083
0084
0085 extern struct pci_ops mace_pci_ops;
0086 #ifdef CONFIG_64BIT
0087 static struct resource mace_pci_mem_resource = {
0088     .name   = "SGI O2 PCI MEM",
0089     .start  = MACEPCI_HI_MEMORY,
0090     .end    = 0x2FFFFFFFFUL,
0091     .flags  = IORESOURCE_MEM,
0092 };
0093 static struct resource mace_pci_io_resource = {
0094     .name   = "SGI O2 PCI IO",
0095     .start  = 0x00000000UL,
0096     .end    = 0xffffffffUL,
0097     .flags  = IORESOURCE_IO,
0098 };
0099 #define MACE_PCI_MEM_OFFSET 0x200000000
0100 #else
0101 static struct resource mace_pci_mem_resource = {
0102     .name   = "SGI O2 PCI MEM",
0103     .start  = MACEPCI_LOW_MEMORY,
0104     .end    = MACEPCI_LOW_MEMORY + 0x2000000 - 1,
0105     .flags  = IORESOURCE_MEM,
0106 };
0107 static struct resource mace_pci_io_resource = {
0108     .name   = "SGI O2 PCI IO",
0109     .start  = 0x00000000,
0110     .end    = 0xFFFFFFFF,
0111     .flags  = IORESOURCE_IO,
0112 };
0113 #define MACE_PCI_MEM_OFFSET (MACEPCI_LOW_MEMORY - 0x80000000)
0114 #endif
0115 static struct pci_controller mace_pci_controller = {
0116     .pci_ops    = &mace_pci_ops,
0117     .mem_resource   = &mace_pci_mem_resource,
0118     .io_resource    = &mace_pci_io_resource,
0119     .mem_offset = MACE_PCI_MEM_OFFSET,
0120     .io_offset  = 0,
0121     .io_map_base    = CKSEG1ADDR(MACEPCI_LOW_IO),
0122 };
0123
0124 static int __init mace_init(void)
0125 {
0126     PCIBIOS_MIN_IO = 0x1000;
0127
0128     /* Clear any outstanding errors and enable interrupts */
0129     mace->pci.error_addr = 0;
0130     mace->pci.error = 0;
0131     mace->pci.control = 0xff008500;
0132
0133     printk("MACE PCI rev %d\n", mace->pci.rev);
0134
0135     BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
0136                "MACE PCI error", NULL));
0137
0138     /* extend memory resources */
0139     iomem_resource.end = mace_pci_mem_resource.end;
0140     ioport_resource = mace_pci_io_resource;
0141
0142     register_pci_controller(&mace_pci_controller);
0143
0144     return 0;
0145 }
0146
0147 arch_initcall(mace_init);