mips/pci/pci-bcm63xx.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
0007  */
0008
0009 #include <linux/types.h>
0010 #include <linux/pci.h>
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/clk.h>
0015 #include <asm/bootinfo.h>
0016
0017 #include <bcm63xx_reset.h>
0018
0019 #include "pci-bcm63xx.h"
0020
0021 /*
0022  * Allow PCI to be disabled at runtime depending on board nvram
0023  * configuration
0024  */
0025 int bcm63xx_pci_enabled;
0026
0027 static struct resource bcm_pci_mem_resource = {
0028     .name   = "bcm63xx PCI memory space",
0029     .start  = BCM_PCI_MEM_BASE_PA,
0030     .end    = BCM_PCI_MEM_END_PA,
0031     .flags  = IORESOURCE_MEM
0032 };
0033
0034 static struct resource bcm_pci_io_resource = {
0035     .name   = "bcm63xx PCI IO space",
0036     .start  = BCM_PCI_IO_BASE_PA,
0037 #ifdef CONFIG_CARDBUS
0038     .end    = BCM_PCI_IO_HALF_PA,
0039 #else
0040     .end    = BCM_PCI_IO_END_PA,
0041 #endif
0042     .flags  = IORESOURCE_IO
0043 };
0044
0045 struct pci_controller bcm63xx_controller = {
0046     .pci_ops    = &bcm63xx_pci_ops,
0047     .io_resource    = &bcm_pci_io_resource,
0048     .mem_resource   = &bcm_pci_mem_resource,
0049 };
0050
0051 /*
0052  * We handle cardbus  via a fake Cardbus bridge,  memory and io spaces
0053  * have to be  clearly separated from PCI one  since we have different
0054  * memory decoder.
0055  */
0056 #ifdef CONFIG_CARDBUS
0057 static struct resource bcm_cb_mem_resource = {
0058     .name   = "bcm63xx Cardbus memory space",
0059     .start  = BCM_CB_MEM_BASE_PA,
0060     .end    = BCM_CB_MEM_END_PA,
0061     .flags  = IORESOURCE_MEM
0062 };
0063
0064 static struct resource bcm_cb_io_resource = {
0065     .name   = "bcm63xx Cardbus IO space",
0066     .start  = BCM_PCI_IO_HALF_PA + 1,
0067     .end    = BCM_PCI_IO_END_PA,
0068     .flags  = IORESOURCE_IO
0069 };
0070
0071 struct pci_controller bcm63xx_cb_controller = {
0072     .pci_ops    = &bcm63xx_cb_ops,
0073     .io_resource    = &bcm_cb_io_resource,
0074     .mem_resource   = &bcm_cb_mem_resource,
0075 };
0076 #endif
0077
0078 static struct resource bcm_pcie_mem_resource = {
0079     .name   = "bcm63xx PCIe memory space",
0080     .start  = BCM_PCIE_MEM_BASE_PA,
0081     .end    = BCM_PCIE_MEM_END_PA,
0082     .flags  = IORESOURCE_MEM,
0083 };
0084
0085 static struct resource bcm_pcie_io_resource = {
0086     .name   = "bcm63xx PCIe IO space",
0087     .start  = 0,
0088     .end    = 0,
0089     .flags  = 0,
0090 };
0091
0092 struct pci_controller bcm63xx_pcie_controller = {
0093     .pci_ops    = &bcm63xx_pcie_ops,
0094     .io_resource    = &bcm_pcie_io_resource,
0095     .mem_resource   = &bcm_pcie_mem_resource,
0096 };
0097
0098 static u32 bcm63xx_int_cfg_readl(u32 reg)
0099 {
0100     u32 tmp;
0101
0102     tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
0103     tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
0104     bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
0105     iob();
0106     return bcm_mpi_readl(MPI_PCICFGDATA_REG);
0107 }
0108
0109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
0110 {
0111     u32 tmp;
0112
0113     tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
0114     tmp |=  MPI_PCICFGCTL_WRITEEN_MASK;
0115     bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
0116     bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
0117 }
0118
0119 void __iomem *pci_iospace_start;
0120
0121 static void __init bcm63xx_reset_pcie(void)
0122 {
0123     u32 val;
0124     u32 reg;
0125
0126     /* enable SERDES */
0127     if (BCMCPU_IS_6328())
0128         reg = MISC_SERDES_CTRL_6328_REG;
0129     else
0130         reg = MISC_SERDES_CTRL_6362_REG;
0131
0132     val = bcm_misc_readl(reg);
0133     val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
0134     bcm_misc_writel(val, reg);
0135
0136     /* reset the PCIe core */
0137     bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
0138     bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
0139     mdelay(10);
0140
0141     bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
0142     mdelay(10);
0143
0144     bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
0145     mdelay(200);
0146 }
0147
0148 static struct clk *pcie_clk;
0149
0150 static int __init bcm63xx_register_pcie(void)
0151 {
0152     u32 val;
0153
0154     /* enable clock */
0155     pcie_clk = clk_get(NULL, "pcie");
0156     if (IS_ERR_OR_NULL(pcie_clk))
0157         return -ENODEV;
0158
0159     clk_prepare_enable(pcie_clk);
0160
0161     bcm63xx_reset_pcie();
0162
0163     /* configure the PCIe bridge */
0164     val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
0165     val |= OPT1_RD_BE_OPT_EN;
0166     val |= OPT1_RD_REPLY_BE_FIX_EN;
0167     val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
0168     val |= OPT1_L1_INT_STATUS_MASK_POL;
0169     bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
0170
0171     /* setup the interrupts */
0172     val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
0173     val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
0174     bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
0175
0176     val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
0177     /* enable credit checking and error checking */
0178     val |= OPT2_TX_CREDIT_CHK_EN;
0179     val |= OPT2_UBUS_UR_DECODE_DIS;
0180
0181     /* set device bus/func for the pcie device */
0182     val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
0183     val |= OPT2_CFG_TYPE1_BD_SEL;
0184     bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
0185
0186     /* setup class code as bridge */
0187     val = bcm_pcie_readl(PCIE_IDVAL3_REG);
0188     val &= ~IDVAL3_CLASS_CODE_MASK;
0189     val |= PCI_CLASS_BRIDGE_PCI_NORMAL;
0190     bcm_pcie_writel(val, PCIE_IDVAL3_REG);
0191
0192     /* disable bar1 size */
0193     val = bcm_pcie_readl(PCIE_CONFIG2_REG);
0194     val &= ~CONFIG2_BAR1_SIZE_MASK;
0195     bcm_pcie_writel(val, PCIE_CONFIG2_REG);
0196
0197     /* set bar0 to little endian */
0198     val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
0199     val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
0200     val |= BASEMASK_REMAP_EN;
0201     bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
0202
0203     val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
0204     bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
0205
0206     register_pci_controller(&bcm63xx_pcie_controller);
0207
0208     return 0;
0209 }
0210
0211 static int __init bcm63xx_register_pci(void)
0212 {
0213     unsigned int mem_size;
0214     u32 val;
0215     /*
0216      * configuration  access are  done through  IO space,  remap 4
0217      * first bytes to access it from CPU.
0218      *
0219      * this means that  no io access from CPU  should happen while
0220      * we do a configuration cycle,  but there's no way we can add
0221      * a spinlock for each io access, so this is currently kind of
0222      * broken on SMP.
0223      */
0224     pci_iospace_start = ioremap(BCM_PCI_IO_BASE_PA, 4);
0225     if (!pci_iospace_start)
0226         return -ENOMEM;
0227
0228     /* setup local bus to PCI access (PCI memory) */
0229     val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
0230     bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
0231     bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
0232     bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
0233
0234     /* set Cardbus IDSEL (type 0 cfg access on primary bus for
0235      * this IDSEL will be done on Cardbus instead) */
0236     val = bcm_pcmcia_readl(PCMCIA_C1_REG);
0237     val &= ~PCMCIA_C1_CBIDSEL_MASK;
0238     val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
0239     bcm_pcmcia_writel(val, PCMCIA_C1_REG);
0240
0241 #ifdef CONFIG_CARDBUS
0242     /* setup local bus to PCI access (Cardbus memory) */
0243     val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
0244     bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
0245     bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
0246     val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
0247     bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
0248 #else
0249     /* disable second access windows */
0250     bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
0251 #endif
0252
0253     /* setup local bus  to PCI access (IO memory),  we have only 1
0254      * IO window  for both PCI  and cardbus, but it  cannot handle
0255      * both  at the  same time,  assume standard  PCI for  now, if
0256      * cardbus card has  IO zone, PCI fixup will  change window to
0257      * cardbus */
0258     val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
0259     bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
0260     bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
0261     bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
0262
0263     /* enable PCI related GPIO pins */
0264     bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
0265
0266     /* setup PCI to local bus access, used by PCI device to target
0267      * local RAM while bus mastering */
0268     bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
0269     if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
0270         val = MPI_SP0_REMAP_ENABLE_MASK;
0271     else
0272         val = 0;
0273     bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
0274
0275     bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
0276     bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
0277
0278     mem_size = bcm63xx_get_memory_size();
0279
0280     /* 6348 before rev b0 exposes only 16 MB of RAM memory through
0281      * PCI, throw a warning if we have more memory */
0282     if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
0283         if (mem_size > (16 * 1024 * 1024))
0284             printk(KERN_WARNING "bcm63xx: this CPU "
0285                    "revision cannot handle more than 16MB "
0286                    "of RAM for PCI bus mastering\n");
0287     } else {
0288         /* setup sp0 range to local RAM size */
0289         bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
0290         bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
0291     }
0292
0293     /* change  host bridge  retry  counter to  infinite number  of
0294      * retry,  needed for  some broadcom  wifi cards  with Silicon
0295      * Backplane bus where access to srom seems very slow  */
0296     val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
0297     val &= ~REG_TIMER_RETRY_MASK;
0298     bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
0299
0300     /* enable memory decoder and bus mastering */
0301     val = bcm63xx_int_cfg_readl(PCI_COMMAND);
0302     val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
0303     bcm63xx_int_cfg_writel(val, PCI_COMMAND);
0304
0305     /* enable read prefetching & disable byte swapping for bus
0306      * mastering transfers */
0307     val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
0308     val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
0309     val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
0310     val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
0311     val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
0312     bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
0313
0314     /* enable pci interrupt */
0315     val = bcm_mpi_readl(MPI_LOCINT_REG);
0316     val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
0317     bcm_mpi_writel(val, MPI_LOCINT_REG);
0318
0319     register_pci_controller(&bcm63xx_controller);
0320
0321 #ifdef CONFIG_CARDBUS
0322     register_pci_controller(&bcm63xx_cb_controller);
0323 #endif
0324
0325     /* mark memory space used for IO mapping as reserved */
0326     request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
0327                "bcm63xx PCI IO space");
0328     return 0;
0329 }
0330
0331
0332 static int __init bcm63xx_pci_init(void)
0333 {
0334     if (!bcm63xx_pci_enabled)
0335         return -ENODEV;
0336
0337     switch (bcm63xx_get_cpu_id()) {
0338     case BCM6328_CPU_ID:
0339     case BCM6362_CPU_ID:
0340         return bcm63xx_register_pcie();
0341     case BCM3368_CPU_ID:
0342     case BCM6348_CPU_ID:
0343     case BCM6358_CPU_ID:
0344     case BCM6368_CPU_ID:
0345         return bcm63xx_register_pci();
0346     default:
0347         return -ENODEV;
0348     }
0349 }
0350
0351 arch_initcall(bcm63xx_pci_init);