mips/pci/pci-bcm1480.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2001,2002,2005 Broadcom Corporation
0004  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
0005  */
0006
0007 /*
0008  * BCM1x80/1x55-specific PCI support
0009  *
0010  * This module provides the glue between Linux's PCI subsystem
0011  * and the hardware.  We basically provide glue for accessing
0012  * configuration space, and set up the translation for I/O
0013  * space accesses.
0014  *
0015  * To access configuration space, we use ioremap.  In the 32-bit
0016  * kernel, this consumes either 4 or 8 page table pages, and 16MB of
0017  * kernel mapped memory.  Hopefully neither of these should be a huge
0018  * problem.
0019  *
0020  * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
0021  */
0022 #include <linux/types.h>
0023 #include <linux/pci.h>
0024 #include <linux/kernel.h>
0025 #include <linux/init.h>
0026 #include <linux/mm.h>
0027 #include <linux/console.h>
0028 #include <linux/tty.h>
0029 #include <linux/vt.h>
0030
0031 #include <asm/sibyte/bcm1480_regs.h>
0032 #include <asm/sibyte/bcm1480_scd.h>
0033 #include <asm/sibyte/board.h>
0034 #include <asm/io.h>
0035
0036 /*
0037  * Macros for calculating offsets into config space given a device
0038  * structure or dev/fun/reg
0039  */
0040 #define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
0041 #define CFGADDR(bus, devfn, where)   CFGOFFSET((bus)->number, (devfn), where)
0042
0043 static void *cfg_space;
0044
0045 #define PCI_BUS_ENABLED 1
0046 #define PCI_DEVICE_MODE 2
0047
0048 static int bcm1480_bus_status;
0049
0050 #define PCI_BRIDGE_DEVICE  0
0051
0052 /*
0053  * Read/write 32-bit values in config space.
0054  */
0055 static inline u32 READCFG32(u32 addr)
0056 {
0057     return *(u32 *)(cfg_space + (addr&~3));
0058 }
0059
0060 static inline void WRITECFG32(u32 addr, u32 data)
0061 {
0062     *(u32 *)(cfg_space + (addr & ~3)) = data;
0063 }
0064
0065 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0066 {
0067     if (pin == 0)
0068         return -1;
0069
0070     return K_BCM1480_INT_PCI_INTA - 1 + pin;
0071 }
0072
0073 /* Do platform specific device initialization at pci_enable_device() time */
0074 int pcibios_plat_dev_init(struct pci_dev *dev)
0075 {
0076     return 0;
0077 }
0078
0079 /*
0080  * Some checks before doing config cycles:
0081  * In PCI Device Mode, hide everything on bus 0 except the LDT host
0082  * bridge.  Otherwise, access is controlled by bridge MasterEn bits.
0083  */
0084 static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
0085 {
0086     u32 devno;
0087
0088     if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
0089         return 0;
0090
0091     if (bus->number == 0) {
0092         devno = PCI_SLOT(devfn);
0093         if (bcm1480_bus_status & PCI_DEVICE_MODE)
0094             return 0;
0095         else
0096             return 1;
0097     } else
0098         return 1;
0099 }
0100
0101 /*
0102  * Read/write access functions for various sizes of values
0103  * in config space.  Return all 1's for disallowed accesses
0104  * for a kludgy but adequate simulation of master aborts.
0105  */
0106
0107 static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
0108                 int where, int size, u32 * val)
0109 {
0110     u32 data = 0;
0111
0112     if ((size == 2) && (where & 1))
0113         return PCIBIOS_BAD_REGISTER_NUMBER;
0114     else if ((size == 4) && (where & 3))
0115         return PCIBIOS_BAD_REGISTER_NUMBER;
0116
0117     if (bcm1480_pci_can_access(bus, devfn))
0118         data = READCFG32(CFGADDR(bus, devfn, where));
0119     else
0120         data = 0xFFFFFFFF;
0121
0122     if (size == 1)
0123         *val = (data >> ((where & 3) << 3)) & 0xff;
0124     else if (size == 2)
0125         *val = (data >> ((where & 3) << 3)) & 0xffff;
0126     else
0127         *val = data;
0128
0129     return PCIBIOS_SUCCESSFUL;
0130 }
0131
0132 static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
0133                 int where, int size, u32 val)
0134 {
0135     u32 cfgaddr = CFGADDR(bus, devfn, where);
0136     u32 data = 0;
0137
0138     if ((size == 2) && (where & 1))
0139         return PCIBIOS_BAD_REGISTER_NUMBER;
0140     else if ((size == 4) && (where & 3))
0141         return PCIBIOS_BAD_REGISTER_NUMBER;
0142
0143     if (!bcm1480_pci_can_access(bus, devfn))
0144         return PCIBIOS_BAD_REGISTER_NUMBER;
0145
0146     data = READCFG32(cfgaddr);
0147
0148     if (size == 1)
0149         data = (data & ~(0xff << ((where & 3) << 3))) |
0150             (val << ((where & 3) << 3));
0151     else if (size == 2)
0152         data = (data & ~(0xffff << ((where & 3) << 3))) |
0153             (val << ((where & 3) << 3));
0154     else
0155         data = val;
0156
0157     WRITECFG32(cfgaddr, data);
0158
0159     return PCIBIOS_SUCCESSFUL;
0160 }
0161
0162 struct pci_ops bcm1480_pci_ops = {
0163     .read   = bcm1480_pcibios_read,
0164     .write  = bcm1480_pcibios_write,
0165 };
0166
0167 static struct resource bcm1480_mem_resource = {
0168     .name   = "BCM1480 PCI MEM",
0169     .start  = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES,
0170     .end    = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES + 0xfffffffUL,
0171     .flags  = IORESOURCE_MEM,
0172 };
0173
0174 static struct resource bcm1480_io_resource = {
0175     .name   = "BCM1480 PCI I/O",
0176     .start  = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
0177     .end    = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES + 0x1ffffffUL,
0178     .flags  = IORESOURCE_IO,
0179 };
0180
0181 struct pci_controller bcm1480_controller = {
0182     .pci_ops    = &bcm1480_pci_ops,
0183     .mem_resource   = &bcm1480_mem_resource,
0184     .io_resource    = &bcm1480_io_resource,
0185     .io_offset  = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
0186 };
0187
0188
0189 static int __init bcm1480_pcibios_init(void)
0190 {
0191     uint32_t cmdreg;
0192     uint64_t reg;
0193
0194     /* CFE will assign PCI resources */
0195     pci_set_flags(PCI_PROBE_ONLY);
0196
0197     /* Avoid ISA compat ranges.  */
0198     PCIBIOS_MIN_IO = 0x00008000UL;
0199     PCIBIOS_MIN_MEM = 0x01000000UL;
0200
0201     /* Set I/O resource limits. - unlimited for now to accommodate HT */
0202     ioport_resource.end = 0xffffffffUL;
0203     iomem_resource.end = 0xffffffffUL;
0204
0205     cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024);
0206
0207     /*
0208      * See if the PCI bus has been configured by the firmware.
0209      */
0210     reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
0211     if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
0212         bcm1480_bus_status |= PCI_DEVICE_MODE;
0213     } else {
0214         cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
0215                          PCI_COMMAND));
0216         if (!(cmdreg & PCI_COMMAND_MASTER)) {
0217             printk
0218                 ("PCI: Skipping PCI probe.  Bus is not initialized.\n");
0219             iounmap(cfg_space);
0220             return 1; /* XXX */
0221         }
0222         bcm1480_bus_status |= PCI_BUS_ENABLED;
0223     }
0224
0225     /* turn on ExpMemEn */
0226     cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
0227     WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
0228             cmdreg | 0x10);
0229     cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
0230
0231     /*
0232      * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
0233      * space.  Use "match bytes" policy to make everything look
0234      * little-endian.  So, you need to also set
0235      * CONFIG_SWAP_IO_SPACE, but this is the combination that
0236      * works correctly with most of Linux's drivers.
0237      * XXX ehs: Should this happen in PCI Device mode?
0238      */
0239
0240     bcm1480_controller.io_map_base = (unsigned long)
0241         ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536);
0242     bcm1480_controller.io_map_base -= bcm1480_controller.io_offset;
0243     set_io_port_base(bcm1480_controller.io_map_base);
0244
0245     register_pci_controller(&bcm1480_controller);
0246
0247 #ifdef CONFIG_VGA_CONSOLE
0248     console_lock();
0249     do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
0250     console_unlock();
0251 #endif
0252     return 0;
0253 }
0254
0255 arch_initcall(bcm1480_pcibios_init);