mips/pci/pci-ar724x.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Atheros AR724X PCI host controller driver
0004  *
0005  *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
0006  *  Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
0007  */
0008
0009 #include <linux/irq.h>
0010 #include <linux/pci.h>
0011 #include <linux/init.h>
0012 #include <linux/delay.h>
0013 #include <linux/platform_device.h>
0014 #include <asm/mach-ath79/ath79.h>
0015 #include <asm/mach-ath79/ar71xx_regs.h>
0016
0017 #define AR724X_PCI_REG_APP      0x00
0018 #define AR724X_PCI_REG_RESET        0x18
0019 #define AR724X_PCI_REG_INT_STATUS   0x4c
0020 #define AR724X_PCI_REG_INT_MASK     0x50
0021
0022 #define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
0023
0024 #define AR724X_PCI_RESET_LINK_UP    BIT(0)
0025
0026 #define AR724X_PCI_INT_DEV0     BIT(14)
0027
0028 #define AR724X_PCI_IRQ_COUNT        1
0029
0030 #define AR7240_BAR0_WAR_VALUE   0xffff
0031
0032 #define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY |       \
0033                  PCI_COMMAND_MASTER |       \
0034                  PCI_COMMAND_INVALIDATE |   \
0035                  PCI_COMMAND_PARITY |       \
0036                  PCI_COMMAND_SERR |     \
0037                  PCI_COMMAND_FAST_BACK)
0038
0039 struct ar724x_pci_controller {
0040     void __iomem *devcfg_base;
0041     void __iomem *ctrl_base;
0042     void __iomem *crp_base;
0043
0044     int irq;
0045     int irq_base;
0046
0047     bool link_up;
0048     bool bar0_is_cached;
0049     u32  bar0_value;
0050
0051     struct pci_controller pci_controller;
0052     struct resource io_res;
0053     struct resource mem_res;
0054 };
0055
0056 static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
0057 {
0058     u32 reset;
0059
0060     reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
0061     return reset & AR724X_PCI_RESET_LINK_UP;
0062 }
0063
0064 static inline struct ar724x_pci_controller *
0065 pci_bus_to_ar724x_controller(struct pci_bus *bus)
0066 {
0067     struct pci_controller *hose;
0068
0069     hose = (struct pci_controller *) bus->sysdata;
0070     return container_of(hose, struct ar724x_pci_controller, pci_controller);
0071 }
0072
0073 static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
0074                   int where, int size, u32 value)
0075 {
0076     void __iomem *base;
0077     u32 data;
0078     int s;
0079
0080     WARN_ON(where & (size - 1));
0081
0082     if (!apc->link_up)
0083         return PCIBIOS_DEVICE_NOT_FOUND;
0084
0085     base = apc->crp_base;
0086     data = __raw_readl(base + (where & ~3));
0087
0088     switch (size) {
0089     case 1:
0090         s = ((where & 3) * 8);
0091         data &= ~(0xff << s);
0092         data |= ((value & 0xff) << s);
0093         break;
0094     case 2:
0095         s = ((where & 2) * 8);
0096         data &= ~(0xffff << s);
0097         data |= ((value & 0xffff) << s);
0098         break;
0099     case 4:
0100         data = value;
0101         break;
0102     default:
0103         return PCIBIOS_BAD_REGISTER_NUMBER;
0104     }
0105
0106     __raw_writel(data, base + (where & ~3));
0107     /* flush write */
0108     __raw_readl(base + (where & ~3));
0109
0110     return PCIBIOS_SUCCESSFUL;
0111 }
0112
0113 static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
0114                 int size, uint32_t *value)
0115 {
0116     struct ar724x_pci_controller *apc;
0117     void __iomem *base;
0118     u32 data;
0119
0120     apc = pci_bus_to_ar724x_controller(bus);
0121     if (!apc->link_up)
0122         return PCIBIOS_DEVICE_NOT_FOUND;
0123
0124     if (devfn)
0125         return PCIBIOS_DEVICE_NOT_FOUND;
0126
0127     base = apc->devcfg_base;
0128     data = __raw_readl(base + (where & ~3));
0129
0130     switch (size) {
0131     case 1:
0132         if (where & 1)
0133             data >>= 8;
0134         if (where & 2)
0135             data >>= 16;
0136         data &= 0xff;
0137         break;
0138     case 2:
0139         if (where & 2)
0140             data >>= 16;
0141         data &= 0xffff;
0142         break;
0143     case 4:
0144         break;
0145     default:
0146         return PCIBIOS_BAD_REGISTER_NUMBER;
0147     }
0148
0149     if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
0150         apc->bar0_is_cached) {
0151         /* use the cached value */
0152         *value = apc->bar0_value;
0153     } else {
0154         *value = data;
0155     }
0156
0157     return PCIBIOS_SUCCESSFUL;
0158 }
0159
0160 static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
0161                  int size, uint32_t value)
0162 {
0163     struct ar724x_pci_controller *apc;
0164     void __iomem *base;
0165     u32 data;
0166     int s;
0167
0168     apc = pci_bus_to_ar724x_controller(bus);
0169     if (!apc->link_up)
0170         return PCIBIOS_DEVICE_NOT_FOUND;
0171
0172     if (devfn)
0173         return PCIBIOS_DEVICE_NOT_FOUND;
0174
0175     if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
0176         if (value != 0xffffffff) {
0177             /*
0178              * WAR for a hw issue. If the BAR0 register of the
0179              * device is set to the proper base address, the
0180              * memory space of the device is not accessible.
0181              *
0182              * Cache the intended value so it can be read back,
0183              * and write a SoC specific constant value to the
0184              * BAR0 register in order to make the device memory
0185              * accessible.
0186              */
0187             apc->bar0_is_cached = true;
0188             apc->bar0_value = value;
0189
0190             value = AR7240_BAR0_WAR_VALUE;
0191         } else {
0192             apc->bar0_is_cached = false;
0193         }
0194     }
0195
0196     base = apc->devcfg_base;
0197     data = __raw_readl(base + (where & ~3));
0198
0199     switch (size) {
0200     case 1:
0201         s = ((where & 3) * 8);
0202         data &= ~(0xff << s);
0203         data |= ((value & 0xff) << s);
0204         break;
0205     case 2:
0206         s = ((where & 2) * 8);
0207         data &= ~(0xffff << s);
0208         data |= ((value & 0xffff) << s);
0209         break;
0210     case 4:
0211         data = value;
0212         break;
0213     default:
0214         return PCIBIOS_BAD_REGISTER_NUMBER;
0215     }
0216
0217     __raw_writel(data, base + (where & ~3));
0218     /* flush write */
0219     __raw_readl(base + (where & ~3));
0220
0221     return PCIBIOS_SUCCESSFUL;
0222 }
0223
0224 static struct pci_ops ar724x_pci_ops = {
0225     .read   = ar724x_pci_read,
0226     .write  = ar724x_pci_write,
0227 };
0228
0229 static void ar724x_pci_irq_handler(struct irq_desc *desc)
0230 {
0231     struct ar724x_pci_controller *apc;
0232     void __iomem *base;
0233     u32 pending;
0234
0235     apc = irq_desc_get_handler_data(desc);
0236     base = apc->ctrl_base;
0237
0238     pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
0239           __raw_readl(base + AR724X_PCI_REG_INT_MASK);
0240
0241     if (pending & AR724X_PCI_INT_DEV0)
0242         generic_handle_irq(apc->irq_base + 0);
0243
0244     else
0245         spurious_interrupt();
0246 }
0247
0248 static void ar724x_pci_irq_unmask(struct irq_data *d)
0249 {
0250     struct ar724x_pci_controller *apc;
0251     void __iomem *base;
0252     int offset;
0253     u32 t;
0254
0255     apc = irq_data_get_irq_chip_data(d);
0256     base = apc->ctrl_base;
0257     offset = apc->irq_base - d->irq;
0258
0259     switch (offset) {
0260     case 0:
0261         t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
0262         __raw_writel(t | AR724X_PCI_INT_DEV0,
0263                  base + AR724X_PCI_REG_INT_MASK);
0264         /* flush write */
0265         __raw_readl(base + AR724X_PCI_REG_INT_MASK);
0266     }
0267 }
0268
0269 static void ar724x_pci_irq_mask(struct irq_data *d)
0270 {
0271     struct ar724x_pci_controller *apc;
0272     void __iomem *base;
0273     int offset;
0274     u32 t;
0275
0276     apc = irq_data_get_irq_chip_data(d);
0277     base = apc->ctrl_base;
0278     offset = apc->irq_base - d->irq;
0279
0280     switch (offset) {
0281     case 0:
0282         t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
0283         __raw_writel(t & ~AR724X_PCI_INT_DEV0,
0284                  base + AR724X_PCI_REG_INT_MASK);
0285
0286         /* flush write */
0287         __raw_readl(base + AR724X_PCI_REG_INT_MASK);
0288
0289         t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
0290         __raw_writel(t | AR724X_PCI_INT_DEV0,
0291                  base + AR724X_PCI_REG_INT_STATUS);
0292
0293         /* flush write */
0294         __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
0295     }
0296 }
0297
0298 static struct irq_chip ar724x_pci_irq_chip = {
0299     .name       = "AR724X PCI ",
0300     .irq_mask   = ar724x_pci_irq_mask,
0301     .irq_unmask = ar724x_pci_irq_unmask,
0302     .irq_mask_ack   = ar724x_pci_irq_mask,
0303 };
0304
0305 static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
0306                 int id)
0307 {
0308     void __iomem *base;
0309     int i;
0310
0311     base = apc->ctrl_base;
0312
0313     __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
0314     __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
0315
0316     apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
0317
0318     for (i = apc->irq_base;
0319          i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
0320         irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
0321                      handle_level_irq);
0322         irq_set_chip_data(i, apc);
0323     }
0324
0325     irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
0326                      apc);
0327 }
0328
0329 static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
0330 {
0331     u32 ppl, app;
0332     int wait = 0;
0333
0334     /* deassert PCIe host controller and PCIe PHY reset */
0335     ath79_device_reset_clear(AR724X_RESET_PCIE);
0336     ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
0337
0338     /* remove the reset of the PCIE PLL */
0339     ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
0340     ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
0341     ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
0342
0343     /* deassert bypass for the PCIE PLL */
0344     ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
0345     ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
0346     ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
0347
0348     /* set PCIE Application Control to ready */
0349     app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
0350     app |= AR724X_PCI_APP_LTSSM_ENABLE;
0351     __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
0352
0353     /* wait up to 100ms for PHY link up */
0354     do {
0355         mdelay(10);
0356         wait++;
0357     } while (wait < 10 && !ar724x_pci_check_link(apc));
0358 }
0359
0360 static int ar724x_pci_probe(struct platform_device *pdev)
0361 {
0362     struct ar724x_pci_controller *apc;
0363     struct resource *res;
0364     int id;
0365
0366     id = pdev->id;
0367     if (id == -1)
0368         id = 0;
0369
0370     apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
0371                 GFP_KERNEL);
0372     if (!apc)
0373         return -ENOMEM;
0374
0375     apc->ctrl_base = devm_platform_ioremap_resource_byname(pdev, "ctrl_base");
0376     if (IS_ERR(apc->ctrl_base))
0377         return PTR_ERR(apc->ctrl_base);
0378
0379     apc->devcfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg_base");
0380     if (IS_ERR(apc->devcfg_base))
0381         return PTR_ERR(apc->devcfg_base);
0382
0383     apc->crp_base = devm_platform_ioremap_resource_byname(pdev, "crp_base");
0384     if (IS_ERR(apc->crp_base))
0385         return PTR_ERR(apc->crp_base);
0386
0387     apc->irq = platform_get_irq(pdev, 0);
0388     if (apc->irq < 0)
0389         return -EINVAL;
0390
0391     res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
0392     if (!res)
0393         return -EINVAL;
0394
0395     apc->io_res.parent = res;
0396     apc->io_res.name = "PCI IO space";
0397     apc->io_res.start = res->start;
0398     apc->io_res.end = res->end;
0399     apc->io_res.flags = IORESOURCE_IO;
0400
0401     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
0402     if (!res)
0403         return -EINVAL;
0404
0405     apc->mem_res.parent = res;
0406     apc->mem_res.name = "PCI memory space";
0407     apc->mem_res.start = res->start;
0408     apc->mem_res.end = res->end;
0409     apc->mem_res.flags = IORESOURCE_MEM;
0410
0411     apc->pci_controller.pci_ops = &ar724x_pci_ops;
0412     apc->pci_controller.io_resource = &apc->io_res;
0413     apc->pci_controller.mem_resource = &apc->mem_res;
0414
0415     /*
0416      * Do the full PCIE Root Complex Initialization Sequence if the PCIe
0417      * host controller is in reset.
0418      */
0419     if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
0420         ar724x_pci_hw_init(apc);
0421
0422     apc->link_up = ar724x_pci_check_link(apc);
0423     if (!apc->link_up)
0424         dev_warn(&pdev->dev, "PCIe link is down\n");
0425
0426     ar724x_pci_irq_init(apc, id);
0427
0428     ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
0429
0430     register_pci_controller(&apc->pci_controller);
0431
0432     return 0;
0433 }
0434
0435 static struct platform_driver ar724x_pci_driver = {
0436     .probe = ar724x_pci_probe,
0437     .driver = {
0438         .name = "ar724x-pci",
0439     },
0440 };
0441
0442 static int __init ar724x_pci_init(void)
0443 {
0444     return platform_driver_register(&ar724x_pci_driver);
0445 }
0446
0447 postcore_initcall(ar724x_pci_init);