mips/pci/pci-ar71xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Atheros AR71xx PCI host controller driver
0004  *
0005  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0006  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0007  *
0008  *  Parts of this file are based on Atheros' 2.6.15 BSP
0009  */
0010
0011 #include <linux/resource.h>
0012 #include <linux/types.h>
0013 #include <linux/delay.h>
0014 #include <linux/bitops.h>
0015 #include <linux/pci.h>
0016 #include <linux/pci_regs.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/init.h>
0019 #include <linux/platform_device.h>
0020
0021 #include <asm/mach-ath79/ar71xx_regs.h>
0022 #include <asm/mach-ath79/ath79.h>
0023
0024 #define AR71XX_PCI_REG_CRP_AD_CBE   0x00
0025 #define AR71XX_PCI_REG_CRP_WRDATA   0x04
0026 #define AR71XX_PCI_REG_CRP_RDDATA   0x08
0027 #define AR71XX_PCI_REG_CFG_AD       0x0c
0028 #define AR71XX_PCI_REG_CFG_CBE      0x10
0029 #define AR71XX_PCI_REG_CFG_WRDATA   0x14
0030 #define AR71XX_PCI_REG_CFG_RDDATA   0x18
0031 #define AR71XX_PCI_REG_PCI_ERR      0x1c
0032 #define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20
0033 #define AR71XX_PCI_REG_AHB_ERR      0x24
0034 #define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28
0035
0036 #define AR71XX_PCI_CRP_CMD_WRITE    0x00010000
0037 #define AR71XX_PCI_CRP_CMD_READ     0x00000000
0038 #define AR71XX_PCI_CFG_CMD_READ     0x0000000a
0039 #define AR71XX_PCI_CFG_CMD_WRITE    0x0000000b
0040
0041 #define AR71XX_PCI_INT_CORE     BIT(4)
0042 #define AR71XX_PCI_INT_DEV2     BIT(2)
0043 #define AR71XX_PCI_INT_DEV1     BIT(1)
0044 #define AR71XX_PCI_INT_DEV0     BIT(0)
0045
0046 #define AR71XX_PCI_IRQ_COUNT        5
0047
0048 struct ar71xx_pci_controller {
0049     void __iomem *cfg_base;
0050     int irq;
0051     int irq_base;
0052     struct pci_controller pci_ctrl;
0053     struct resource io_res;
0054     struct resource mem_res;
0055 };
0056
0057 /* Byte lane enable bits */
0058 static const u8 ar71xx_pci_ble_table[4][4] = {
0059     {0x0, 0xf, 0xf, 0xf},
0060     {0xe, 0xd, 0xb, 0x7},
0061     {0xc, 0xf, 0x3, 0xf},
0062     {0xf, 0xf, 0xf, 0xf},
0063 };
0064
0065 static const u32 ar71xx_pci_read_mask[8] = {
0066     0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
0067 };
0068
0069 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
0070 {
0071     u32 t;
0072
0073     t = ar71xx_pci_ble_table[size & 3][where & 3];
0074     BUG_ON(t == 0xf);
0075     t <<= (local) ? 20 : 4;
0076
0077     return t;
0078 }
0079
0080 static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
0081                       int where)
0082 {
0083     u32 ret;
0084
0085     if (!bus->number) {
0086         /* type 0 */
0087         ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
0088               (where & ~3);
0089     } else {
0090         /* type 1 */
0091         ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
0092               (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
0093     }
0094
0095     return ret;
0096 }
0097
0098 static inline struct ar71xx_pci_controller *
0099 pci_bus_to_ar71xx_controller(struct pci_bus *bus)
0100 {
0101     struct pci_controller *hose;
0102
0103     hose = (struct pci_controller *) bus->sysdata;
0104     return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
0105 }
0106
0107 static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
0108 {
0109     void __iomem *base = apc->cfg_base;
0110     u32 pci_err;
0111     u32 ahb_err;
0112
0113     pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
0114     if (pci_err) {
0115         if (!quiet) {
0116             u32 addr;
0117
0118             addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
0119             pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
0120                 "PCI", pci_err, addr);
0121         }
0122
0123         /* clear PCI error status */
0124         __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
0125     }
0126
0127     ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
0128     if (ahb_err) {
0129         if (!quiet) {
0130             u32 addr;
0131
0132             addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
0133             pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
0134                 "AHB", ahb_err, addr);
0135         }
0136
0137         /* clear AHB error status */
0138         __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
0139     }
0140
0141     return !!(ahb_err | pci_err);
0142 }
0143
0144 static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
0145                       int where, int size, u32 value)
0146 {
0147     void __iomem *base = apc->cfg_base;
0148     u32 ad_cbe;
0149
0150     value = value << (8 * (where & 3));
0151
0152     ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
0153     ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
0154
0155     __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
0156     __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
0157 }
0158
0159 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
0160                      unsigned int devfn,
0161                      int where, int size, u32 cmd)
0162 {
0163     struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
0164     void __iomem *base = apc->cfg_base;
0165     u32 addr;
0166
0167     addr = ar71xx_pci_bus_addr(bus, devfn, where);
0168
0169     __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
0170     __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
0171              base + AR71XX_PCI_REG_CFG_CBE);
0172
0173     return ar71xx_pci_check_error(apc, 1);
0174 }
0175
0176 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
0177                   int where, int size, u32 *value)
0178 {
0179     struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
0180     void __iomem *base = apc->cfg_base;
0181     u32 data;
0182     int err;
0183     int ret;
0184
0185     ret = PCIBIOS_SUCCESSFUL;
0186     data = ~0;
0187
0188     err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
0189                      AR71XX_PCI_CFG_CMD_READ);
0190     if (err)
0191         ret = PCIBIOS_DEVICE_NOT_FOUND;
0192     else
0193         data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
0194
0195     *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
0196
0197     return ret;
0198 }
0199
0200 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
0201                    int where, int size, u32 value)
0202 {
0203     struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
0204     void __iomem *base = apc->cfg_base;
0205     int err;
0206     int ret;
0207
0208     value = value << (8 * (where & 3));
0209     ret = PCIBIOS_SUCCESSFUL;
0210
0211     err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
0212                      AR71XX_PCI_CFG_CMD_WRITE);
0213     if (err)
0214         ret = PCIBIOS_DEVICE_NOT_FOUND;
0215     else
0216         __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
0217
0218     return ret;
0219 }
0220
0221 static struct pci_ops ar71xx_pci_ops = {
0222     .read   = ar71xx_pci_read_config,
0223     .write  = ar71xx_pci_write_config,
0224 };
0225
0226 static void ar71xx_pci_irq_handler(struct irq_desc *desc)
0227 {
0228     struct ar71xx_pci_controller *apc;
0229     void __iomem *base = ath79_reset_base;
0230     u32 pending;
0231
0232     apc = irq_desc_get_handler_data(desc);
0233
0234     pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
0235           __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
0236
0237     if (pending & AR71XX_PCI_INT_DEV0)
0238         generic_handle_irq(apc->irq_base + 0);
0239
0240     else if (pending & AR71XX_PCI_INT_DEV1)
0241         generic_handle_irq(apc->irq_base + 1);
0242
0243     else if (pending & AR71XX_PCI_INT_DEV2)
0244         generic_handle_irq(apc->irq_base + 2);
0245
0246     else if (pending & AR71XX_PCI_INT_CORE)
0247         generic_handle_irq(apc->irq_base + 4);
0248
0249     else
0250         spurious_interrupt();
0251 }
0252
0253 static void ar71xx_pci_irq_unmask(struct irq_data *d)
0254 {
0255     struct ar71xx_pci_controller *apc;
0256     unsigned int irq;
0257     void __iomem *base = ath79_reset_base;
0258     u32 t;
0259
0260     apc = irq_data_get_irq_chip_data(d);
0261     irq = d->irq - apc->irq_base;
0262
0263     t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
0264     __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
0265
0266     /* flush write */
0267     __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
0268 }
0269
0270 static void ar71xx_pci_irq_mask(struct irq_data *d)
0271 {
0272     struct ar71xx_pci_controller *apc;
0273     unsigned int irq;
0274     void __iomem *base = ath79_reset_base;
0275     u32 t;
0276
0277     apc = irq_data_get_irq_chip_data(d);
0278     irq = d->irq - apc->irq_base;
0279
0280     t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
0281     __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
0282
0283     /* flush write */
0284     __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
0285 }
0286
0287 static struct irq_chip ar71xx_pci_irq_chip = {
0288     .name       = "AR71XX PCI",
0289     .irq_mask   = ar71xx_pci_irq_mask,
0290     .irq_unmask = ar71xx_pci_irq_unmask,
0291     .irq_mask_ack   = ar71xx_pci_irq_mask,
0292 };
0293
0294 static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
0295 {
0296     void __iomem *base = ath79_reset_base;
0297     int i;
0298
0299     __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
0300     __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
0301
0302     BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
0303
0304     apc->irq_base = ATH79_PCI_IRQ_BASE;
0305     for (i = apc->irq_base;
0306          i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
0307         irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
0308                      handle_level_irq);
0309         irq_set_chip_data(i, apc);
0310     }
0311
0312     irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
0313                      apc);
0314 }
0315
0316 static void ar71xx_pci_reset(void)
0317 {
0318     ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
0319     mdelay(100);
0320
0321     ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
0322     mdelay(100);
0323
0324     ath79_ddr_set_pci_windows();
0325     mdelay(100);
0326 }
0327
0328 static int ar71xx_pci_probe(struct platform_device *pdev)
0329 {
0330     struct ar71xx_pci_controller *apc;
0331     struct resource *res;
0332     u32 t;
0333
0334     apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
0335                GFP_KERNEL);
0336     if (!apc)
0337         return -ENOMEM;
0338
0339     apc->cfg_base = devm_platform_ioremap_resource_byname(pdev,
0340                                   "cfg_base");
0341     if (IS_ERR(apc->cfg_base))
0342         return PTR_ERR(apc->cfg_base);
0343
0344     apc->irq = platform_get_irq(pdev, 0);
0345     if (apc->irq < 0)
0346         return -EINVAL;
0347
0348     res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
0349     if (!res)
0350         return -EINVAL;
0351
0352     apc->io_res.parent = res;
0353     apc->io_res.name = "PCI IO space";
0354     apc->io_res.start = res->start;
0355     apc->io_res.end = res->end;
0356     apc->io_res.flags = IORESOURCE_IO;
0357
0358     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
0359     if (!res)
0360         return -EINVAL;
0361
0362     apc->mem_res.parent = res;
0363     apc->mem_res.name = "PCI memory space";
0364     apc->mem_res.start = res->start;
0365     apc->mem_res.end = res->end;
0366     apc->mem_res.flags = IORESOURCE_MEM;
0367
0368     ar71xx_pci_reset();
0369
0370     /* setup COMMAND register */
0371     t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
0372       | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
0373     ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
0374
0375     /* clear bus errors */
0376     ar71xx_pci_check_error(apc, 1);
0377
0378     ar71xx_pci_irq_init(apc);
0379
0380     apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
0381     apc->pci_ctrl.mem_resource = &apc->mem_res;
0382     apc->pci_ctrl.io_resource = &apc->io_res;
0383
0384     register_pci_controller(&apc->pci_ctrl);
0385
0386     return 0;
0387 }
0388
0389 static struct platform_driver ar71xx_pci_driver = {
0390     .probe = ar71xx_pci_probe,
0391     .driver = {
0392         .name = "ar71xx-pci",
0393     },
0394 };
0395
0396 static int __init ar71xx_pci_init(void)
0397 {
0398     return platform_driver_register(&ar71xx_pci_driver);
0399 }
0400
0401 postcore_initcall(ar71xx_pci_init);