mips/pci/pci-ar2315.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  */
0004
0005 /**
0006  * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
0007  * and interrupt. PCI interface supports MMIO access method, but does not
0008  * seem to support I/O ports.
0009  *
0010  * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
0011  * a memory read/write command on the PCI bus. 30 LSBs of address on
0012  * the bus are taken from memory read/write request and 2 MSBs are
0013  * determined by PCI unit configuration.
0014  *
0015  * To work with the configuration space instead of memory is necessary set
0016  * the CFG_SEL bit in the PCI_MISC_CONFIG register.
0017  *
0018  * Devices on the bus can perform DMA requests via chip BAR1. PCI host
0019  * controller BARs are programmend as if an external device is programmed.
0020  * Which means that during configuration, IDSEL pin of the chip should be
0021  * asserted.
0022  *
0023  * We know (and support) only one board that uses the PCI interface -
0024  * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
0025  * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
0026  * and IDSEL pin of AR2315 is connected to AD[16] line.
0027  */
0028
0029 #include <linux/types.h>
0030 #include <linux/pci.h>
0031 #include <linux/platform_device.h>
0032 #include <linux/kernel.h>
0033 #include <linux/init.h>
0034 #include <linux/dma-direct.h>
0035 #include <linux/mm.h>
0036 #include <linux/delay.h>
0037 #include <linux/bitops.h>
0038 #include <linux/irq.h>
0039 #include <linux/irqdomain.h>
0040 #include <linux/io.h>
0041 #include <asm/paccess.h>
0042
0043 /*
0044  * PCI Bus Interface Registers
0045  */
0046 #define AR2315_PCI_1MS_REG      0x0008
0047
0048 #define AR2315_PCI_1MS_MASK     0x3FFFF /* # of AHB clk cycles in 1ms */
0049
0050 #define AR2315_PCI_MISC_CONFIG      0x000c
0051
0052 #define AR2315_PCIMISC_TXD_EN   0x00000001  /* Enable TXD for fragments */
0053 #define AR2315_PCIMISC_CFG_SEL  0x00000002  /* Mem or Config cycles */
0054 #define AR2315_PCIMISC_GIG_MASK 0x0000000C  /* bits 31-30 for pci req */
0055 #define AR2315_PCIMISC_RST_MODE 0x00000030
0056 #define AR2315_PCIRST_INPUT 0x00000000  /* 4:5=0 rst is input */
0057 #define AR2315_PCIRST_LOW   0x00000010  /* 4:5=1 rst to GND */
0058 #define AR2315_PCIRST_HIGH  0x00000020  /* 4:5=2 rst to VDD */
0059 #define AR2315_PCIGRANT_EN  0x00000000  /* 6:7=0 early grant en */
0060 #define AR2315_PCIGRANT_FRAME   0x00000040  /* 6:7=1 grant waits 4 frame */
0061 #define AR2315_PCIGRANT_IDLE    0x00000080  /* 6:7=2 grant waits 4 idle */
0062 #define AR2315_PCIGRANT_GAP 0x00000000  /* 6:7=2 grant waits 4 idle */
0063 #define AR2315_PCICACHE_DIS 0x00001000  /* PCI external access cache
0064                          * disable */
0065
0066 #define AR2315_PCI_OUT_TSTAMP       0x0010
0067
0068 #define AR2315_PCI_UNCACHE_CFG      0x0014
0069
0070 #define AR2315_PCI_IN_EN        0x0100
0071
0072 #define AR2315_PCI_IN_EN0   0x01    /* Enable chain 0 */
0073 #define AR2315_PCI_IN_EN1   0x02    /* Enable chain 1 */
0074 #define AR2315_PCI_IN_EN2   0x04    /* Enable chain 2 */
0075 #define AR2315_PCI_IN_EN3   0x08    /* Enable chain 3 */
0076
0077 #define AR2315_PCI_IN_DIS       0x0104
0078
0079 #define AR2315_PCI_IN_DIS0  0x01    /* Disable chain 0 */
0080 #define AR2315_PCI_IN_DIS1  0x02    /* Disable chain 1 */
0081 #define AR2315_PCI_IN_DIS2  0x04    /* Disable chain 2 */
0082 #define AR2315_PCI_IN_DIS3  0x08    /* Disable chain 3 */
0083
0084 #define AR2315_PCI_IN_PTR       0x0200
0085
0086 #define AR2315_PCI_OUT_EN       0x0400
0087
0088 #define AR2315_PCI_OUT_EN0  0x01    /* Enable chain 0 */
0089
0090 #define AR2315_PCI_OUT_DIS      0x0404
0091
0092 #define AR2315_PCI_OUT_DIS0 0x01    /* Disable chain 0 */
0093
0094 #define AR2315_PCI_OUT_PTR      0x0408
0095
0096 /* PCI interrupt status (write one to clear) */
0097 #define AR2315_PCI_ISR          0x0500
0098
0099 #define AR2315_PCI_INT_TX   0x00000001  /* Desc In Completed */
0100 #define AR2315_PCI_INT_TXOK 0x00000002  /* Desc In OK */
0101 #define AR2315_PCI_INT_TXERR    0x00000004  /* Desc In ERR */
0102 #define AR2315_PCI_INT_TXEOL    0x00000008  /* Desc In End-of-List */
0103 #define AR2315_PCI_INT_RX   0x00000010  /* Desc Out Completed */
0104 #define AR2315_PCI_INT_RXOK 0x00000020  /* Desc Out OK */
0105 #define AR2315_PCI_INT_RXERR    0x00000040  /* Desc Out ERR */
0106 #define AR2315_PCI_INT_RXEOL    0x00000080  /* Desc Out EOL */
0107 #define AR2315_PCI_INT_TXOOD    0x00000200  /* Desc In Out-of-Desc */
0108 #define AR2315_PCI_INT_DESCMASK 0x0000FFFF  /* Desc Mask */
0109 #define AR2315_PCI_INT_EXT  0x02000000  /* Extern PCI INTA */
0110 #define AR2315_PCI_INT_ABORT    0x04000000  /* PCI bus abort event */
0111
0112 /* PCI interrupt mask */
0113 #define AR2315_PCI_IMR          0x0504
0114
0115 /* Global PCI interrupt enable */
0116 #define AR2315_PCI_IER          0x0508
0117
0118 #define AR2315_PCI_IER_DISABLE      0x00    /* disable pci interrupts */
0119 #define AR2315_PCI_IER_ENABLE       0x01    /* enable pci interrupts */
0120
0121 #define AR2315_PCI_HOST_IN_EN       0x0800
0122 #define AR2315_PCI_HOST_IN_DIS      0x0804
0123 #define AR2315_PCI_HOST_IN_PTR      0x0810
0124 #define AR2315_PCI_HOST_OUT_EN      0x0900
0125 #define AR2315_PCI_HOST_OUT_DIS     0x0904
0126 #define AR2315_PCI_HOST_OUT_PTR     0x0908
0127
0128 /*
0129  * PCI interrupts, which share IP5
0130  * Keep ordered according to AR2315_PCI_INT_XXX bits
0131  */
0132 #define AR2315_PCI_IRQ_EXT      25
0133 #define AR2315_PCI_IRQ_ABORT        26
0134 #define AR2315_PCI_IRQ_COUNT        27
0135
0136 /* Arbitrary size of memory region to access the configuration space */
0137 #define AR2315_PCI_CFG_SIZE 0x00100000
0138
0139 #define AR2315_PCI_HOST_SLOT    3
0140 #define AR2315_PCI_HOST_DEVID   ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
0141
0142 /*
0143  * We need some arbitrary non-zero value to be programmed to the BAR1 register
0144  * of PCI host controller to enable DMA. The same value should be used as the
0145  * offset to calculate the physical address of DMA buffer for PCI devices.
0146  */
0147 #define AR2315_PCI_HOST_SDRAM_BASEADDR  0x20000000
0148
0149 /* ??? access BAR */
0150 #define AR2315_PCI_HOST_MBAR0       0x10000000
0151 /* RAM access BAR */
0152 #define AR2315_PCI_HOST_MBAR1       AR2315_PCI_HOST_SDRAM_BASEADDR
0153 /* ??? access BAR */
0154 #define AR2315_PCI_HOST_MBAR2       0x30000000
0155
0156 struct ar2315_pci_ctrl {
0157     void __iomem *cfg_mem;
0158     void __iomem *mmr_mem;
0159     unsigned irq;
0160     unsigned irq_ext;
0161     struct irq_domain *domain;
0162     struct pci_controller pci_ctrl;
0163     struct resource mem_res;
0164     struct resource io_res;
0165 };
0166
0167 static inline dma_addr_t ar2315_dev_offset(struct device *dev)
0168 {
0169     if (dev && dev_is_pci(dev))
0170         return AR2315_PCI_HOST_SDRAM_BASEADDR;
0171     return 0;
0172 }
0173
0174 dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
0175 {
0176     return paddr + ar2315_dev_offset(dev);
0177 }
0178
0179 phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
0180 {
0181     return dma_addr - ar2315_dev_offset(dev);
0182 }
0183
0184 static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
0185 {
0186     struct pci_controller *hose = bus->sysdata;
0187
0188     return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
0189 }
0190
0191 static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
0192 {
0193     return __raw_readl(apc->mmr_mem + reg);
0194 }
0195
0196 static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
0197                     u32 val)
0198 {
0199     __raw_writel(val, apc->mmr_mem + reg);
0200 }
0201
0202 static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
0203                        u32 mask, u32 val)
0204 {
0205     u32 ret = ar2315_pci_reg_read(apc, reg);
0206
0207     ret &= ~mask;
0208     ret |= val;
0209     ar2315_pci_reg_write(apc, reg, ret);
0210 }
0211
0212 static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
0213                  int where, int size, u32 *ptr, bool write)
0214 {
0215     int func = PCI_FUNC(devfn);
0216     int dev = PCI_SLOT(devfn);
0217     u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
0218     u32 mask = 0xffffffff >> 8 * (4 - size);
0219     u32 sh = (where & 3) * 8;
0220     u32 value, isr;
0221
0222     /* Prevent access past the remapped area */
0223     if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
0224         return PCIBIOS_DEVICE_NOT_FOUND;
0225
0226     /* Clear pending errors */
0227     ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
0228     /* Select Configuration access */
0229     ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
0230                 AR2315_PCIMISC_CFG_SEL);
0231
0232     mb();   /* PCI must see space change before we begin */
0233
0234     value = __raw_readl(apc->cfg_mem + addr);
0235
0236     isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
0237
0238     if (isr & AR2315_PCI_INT_ABORT)
0239         goto exit_err;
0240
0241     if (write) {
0242         value = (value & ~(mask << sh)) | *ptr << sh;
0243         __raw_writel(value, apc->cfg_mem + addr);
0244         isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
0245         if (isr & AR2315_PCI_INT_ABORT)
0246             goto exit_err;
0247     } else {
0248         *ptr = (value >> sh) & mask;
0249     }
0250
0251     goto exit;
0252
0253 exit_err:
0254     ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
0255     if (!write)
0256         *ptr = 0xffffffff;
0257
0258 exit:
0259     /* Select Memory access */
0260     ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
0261                 0);
0262
0263     return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
0264                         PCIBIOS_SUCCESSFUL;
0265 }
0266
0267 static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
0268                       unsigned devfn, int where, u32 *val)
0269 {
0270     return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
0271                      false);
0272 }
0273
0274 static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
0275                       unsigned devfn, int where, u32 val)
0276 {
0277     return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
0278                      true);
0279 }
0280
0281 static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
0282                    int size, u32 *value)
0283 {
0284     struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
0285
0286     if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
0287         return PCIBIOS_DEVICE_NOT_FOUND;
0288
0289     return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
0290 }
0291
0292 static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
0293                 int size, u32 value)
0294 {
0295     struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
0296
0297     if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
0298         return PCIBIOS_DEVICE_NOT_FOUND;
0299
0300     return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
0301 }
0302
0303 static struct pci_ops ar2315_pci_ops = {
0304     .read   = ar2315_pci_cfg_read,
0305     .write  = ar2315_pci_cfg_write,
0306 };
0307
0308 static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
0309 {
0310     unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
0311     int res;
0312     u32 id;
0313
0314     res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
0315     if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
0316         return -ENODEV;
0317
0318     /* Program MBARs */
0319     ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
0320                 AR2315_PCI_HOST_MBAR0);
0321     ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
0322                 AR2315_PCI_HOST_MBAR1);
0323     ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
0324                 AR2315_PCI_HOST_MBAR2);
0325
0326     /* Run */
0327     ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
0328                 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
0329                 PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
0330                 PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
0331
0332     return 0;
0333 }
0334
0335 static void ar2315_pci_irq_handler(struct irq_desc *desc)
0336 {
0337     struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
0338     u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
0339               ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
0340     int ret = 0;
0341
0342     if (pending)
0343         ret = generic_handle_domain_irq(apc->domain, __ffs(pending));
0344
0345     if (!pending || ret)
0346         spurious_interrupt();
0347 }
0348
0349 static void ar2315_pci_irq_mask(struct irq_data *d)
0350 {
0351     struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
0352
0353     ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
0354 }
0355
0356 static void ar2315_pci_irq_mask_ack(struct irq_data *d)
0357 {
0358     struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
0359     u32 m = BIT(d->hwirq);
0360
0361     ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
0362     ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
0363 }
0364
0365 static void ar2315_pci_irq_unmask(struct irq_data *d)
0366 {
0367     struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
0368
0369     ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
0370 }
0371
0372 static struct irq_chip ar2315_pci_irq_chip = {
0373     .name = "AR2315-PCI",
0374     .irq_mask = ar2315_pci_irq_mask,
0375     .irq_mask_ack = ar2315_pci_irq_mask_ack,
0376     .irq_unmask = ar2315_pci_irq_unmask,
0377 };
0378
0379 static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
0380                   irq_hw_number_t hw)
0381 {
0382     irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
0383     irq_set_chip_data(irq, d->host_data);
0384     return 0;
0385 }
0386
0387 static const struct irq_domain_ops ar2315_pci_irq_domain_ops = {
0388     .map = ar2315_pci_irq_map,
0389 };
0390
0391 static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
0392 {
0393     ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
0394     ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
0395                 AR2315_PCI_INT_EXT), 0);
0396
0397     apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
0398
0399     irq_set_chained_handler_and_data(apc->irq, ar2315_pci_irq_handler,
0400                      apc);
0401
0402     /* Clear any pending Abort or external Interrupts
0403      * and enable interrupt processing */
0404     ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
0405                           AR2315_PCI_INT_EXT);
0406     ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
0407 }
0408
0409 static int ar2315_pci_probe(struct platform_device *pdev)
0410 {
0411     struct ar2315_pci_ctrl *apc;
0412     struct device *dev = &pdev->dev;
0413     struct resource *res;
0414     int irq, err;
0415
0416     apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
0417     if (!apc)
0418         return -ENOMEM;
0419
0420     irq = platform_get_irq(pdev, 0);
0421     if (irq < 0)
0422         return -EINVAL;
0423     apc->irq = irq;
0424
0425     apc->mmr_mem = devm_platform_ioremap_resource_byname(pdev,
0426                                  "ar2315-pci-ctrl");
0427     if (IS_ERR(apc->mmr_mem))
0428         return PTR_ERR(apc->mmr_mem);
0429
0430     res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
0431                        "ar2315-pci-ext");
0432     if (!res)
0433         return -EINVAL;
0434
0435     apc->mem_res.name = "AR2315 PCI mem space";
0436     apc->mem_res.parent = res;
0437     apc->mem_res.start = res->start;
0438     apc->mem_res.end = res->end;
0439     apc->mem_res.flags = IORESOURCE_MEM;
0440
0441     /* Remap PCI config space */
0442     apc->cfg_mem = devm_ioremap(dev, res->start,
0443                         AR2315_PCI_CFG_SIZE);
0444     if (!apc->cfg_mem) {
0445         dev_err(dev, "failed to remap PCI config space\n");
0446         return -ENOMEM;
0447     }
0448
0449     /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
0450     ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
0451                 AR2315_PCIMISC_RST_MODE,
0452                 AR2315_PCIRST_LOW);
0453     msleep(100);
0454
0455     /* Bring the PCI out of reset */
0456     ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
0457                 AR2315_PCIMISC_RST_MODE,
0458                 AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
0459
0460     ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
0461                  0x1E | /* 1GB uncached */
0462                  (1 << 5) | /* Enable uncached */
0463                  (0x2 << 30) /* Base: 0x80000000 */);
0464     ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
0465
0466     msleep(500);
0467
0468     err = ar2315_pci_host_setup(apc);
0469     if (err)
0470         return err;
0471
0472     apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
0473                         &ar2315_pci_irq_domain_ops, apc);
0474     if (!apc->domain) {
0475         dev_err(dev, "failed to add IRQ domain\n");
0476         return -ENOMEM;
0477     }
0478
0479     ar2315_pci_irq_init(apc);
0480
0481     /* PCI controller does not support I/O ports */
0482     apc->io_res.name = "AR2315 IO space";
0483     apc->io_res.start = 0;
0484     apc->io_res.end = 0;
0485     apc->io_res.flags = IORESOURCE_IO;
0486
0487     apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
0488     apc->pci_ctrl.mem_resource = &apc->mem_res;
0489     apc->pci_ctrl.io_resource = &apc->io_res;
0490
0491     register_pci_controller(&apc->pci_ctrl);
0492
0493     dev_info(dev, "register PCI controller\n");
0494
0495     return 0;
0496 }
0497
0498 static struct platform_driver ar2315_pci_driver = {
0499     .probe = ar2315_pci_probe,
0500     .driver = {
0501         .name = "ar2315-pci",
0502     },
0503 };
0504
0505 static int __init ar2315_pci_init(void)
0506 {
0507     return platform_driver_register(&ar2315_pci_driver);
0508 }
0509 arch_initcall(ar2315_pci_init);
0510
0511 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0512 {
0513     struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
0514
0515     return slot ? 0 : apc->irq_ext;
0516 }
0517
0518 int pcibios_plat_dev_init(struct pci_dev *dev)
0519 {
0520     return 0;
0521 }