mips/pci/pci-alchemy.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Alchemy PCI host mode support.
0004  *
0005  * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
0006  * Author: MontaVista Software, Inc. <source@mvista.com>
0007  *
0008  * Support for all devices (greater than 16) added by David Gathright.
0009  */
0010
0011 #include <linux/clk.h>
0012 #include <linux/export.h>
0013 #include <linux/types.h>
0014 #include <linux/pci.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/kernel.h>
0017 #include <linux/init.h>
0018 #include <linux/syscore_ops.h>
0019 #include <linux/vmalloc.h>
0020 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
0021
0022 #include <asm/mach-au1x00/au1000.h>
0023 #include <asm/tlbmisc.h>
0024
0025 #ifdef CONFIG_PCI_DEBUG
0026 #define DBG(x...) printk(KERN_DEBUG x)
0027 #else
0028 #define DBG(x...) do {} while (0)
0029 #endif
0030
0031 #define PCI_ACCESS_READ     0
0032 #define PCI_ACCESS_WRITE    1
0033
0034 struct alchemy_pci_context {
0035     struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
0036     void __iomem *regs;         /* ctrl base */
0037     /* tools for wired entry for config space access */
0038     unsigned long last_elo0;
0039     unsigned long last_elo1;
0040     int wired_entry;
0041     struct vm_struct *pci_cfg_vm;
0042
0043     unsigned long pm[12];
0044
0045     int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
0046     int (*board_pci_idsel)(unsigned int devsel, int assert);
0047 };
0048
0049 /* for syscore_ops. There's only one PCI controller on Alchemy chips, so this
0050  * should suffice for now.
0051  */
0052 static struct alchemy_pci_context *__alchemy_pci_ctx;
0053
0054
0055 /* IO/MEM resources for PCI. Keep the memres in sync with fixup_bigphys_addr
0056  * in arch/mips/alchemy/common/setup.c
0057  */
0058 static struct resource alchemy_pci_def_memres = {
0059     .start  = ALCHEMY_PCI_MEMWIN_START,
0060     .end    = ALCHEMY_PCI_MEMWIN_END,
0061     .name   = "PCI memory space",
0062     .flags  = IORESOURCE_MEM
0063 };
0064
0065 static struct resource alchemy_pci_def_iores = {
0066     .start  = ALCHEMY_PCI_IOWIN_START,
0067     .end    = ALCHEMY_PCI_IOWIN_END,
0068     .name   = "PCI IO space",
0069     .flags  = IORESOURCE_IO
0070 };
0071
0072 static void mod_wired_entry(int entry, unsigned long entrylo0,
0073         unsigned long entrylo1, unsigned long entryhi,
0074         unsigned long pagemask)
0075 {
0076     unsigned long old_pagemask;
0077     unsigned long old_ctx;
0078
0079     /* Save old context and create impossible VPN2 value */
0080     old_ctx = read_c0_entryhi() & MIPS_ENTRYHI_ASID;
0081     old_pagemask = read_c0_pagemask();
0082     write_c0_index(entry);
0083     write_c0_pagemask(pagemask);
0084     write_c0_entryhi(entryhi);
0085     write_c0_entrylo0(entrylo0);
0086     write_c0_entrylo1(entrylo1);
0087     tlb_write_indexed();
0088     write_c0_entryhi(old_ctx);
0089     write_c0_pagemask(old_pagemask);
0090 }
0091
0092 static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx)
0093 {
0094     ctx->wired_entry = read_c0_wired();
0095     add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
0096     ctx->last_elo0 = ctx->last_elo1 = ~0;
0097 }
0098
0099 static int config_access(unsigned char access_type, struct pci_bus *bus,
0100              unsigned int dev_fn, unsigned char where, u32 *data)
0101 {
0102     struct alchemy_pci_context *ctx = bus->sysdata;
0103     unsigned int device = PCI_SLOT(dev_fn);
0104     unsigned int function = PCI_FUNC(dev_fn);
0105     unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r;
0106     int error = PCIBIOS_SUCCESSFUL;
0107
0108     if (device > 19) {
0109         *data = 0xffffffff;
0110         return -1;
0111     }
0112
0113     local_irq_save(flags);
0114     r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
0115     r |= PCI_STATCMD_STATUS(0x2000);
0116     __raw_writel(r, ctx->regs + PCI_REG_STATCMD);
0117     wmb();
0118
0119     /* Allow board vendors to implement their own off-chip IDSEL.
0120      * If it doesn't succeed, may as well bail out at this point.
0121      */
0122     if (ctx->board_pci_idsel(device, 1) == 0) {
0123         *data = 0xffffffff;
0124         local_irq_restore(flags);
0125         return -1;
0126     }
0127
0128     /* Setup the config window */
0129     if (bus->number == 0)
0130         cfg_base = (1 << device) << 11;
0131     else
0132         cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
0133
0134     /* Setup the lower bits of the 36-bit address */
0135     offset = (function << 8) | (where & ~0x3);
0136     /* Pick up any address that falls below the page mask */
0137     offset |= cfg_base & ~PAGE_MASK;
0138
0139     /* Page boundary */
0140     cfg_base = cfg_base & PAGE_MASK;
0141
0142     /* To improve performance, if the current device is the same as
0143      * the last device accessed, we don't touch the TLB.
0144      */
0145     entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
0146     entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
0147     if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) {
0148         mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1,
0149                 (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
0150         ctx->last_elo0 = entryLo0;
0151         ctx->last_elo1 = entryLo1;
0152     }
0153
0154     if (access_type == PCI_ACCESS_WRITE)
0155         __raw_writel(*data, ctx->pci_cfg_vm->addr + offset);
0156     else
0157         *data = __raw_readl(ctx->pci_cfg_vm->addr + offset);
0158     wmb();
0159
0160     DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n",
0161         access_type, bus->number, device, where, *data, offset);
0162
0163     /* check for errors, master abort */
0164     status = __raw_readl(ctx->regs + PCI_REG_STATCMD);
0165     if (status & (1 << 29)) {
0166         *data = 0xffffffff;
0167         error = -1;
0168         DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
0169             access_type, bus->number, device);
0170     } else if ((status >> 28) & 0xf) {
0171         DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
0172             device, (status >> 28) & 0xf);
0173
0174         /* clear errors */
0175         __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD);
0176
0177         *data = 0xffffffff;
0178         error = -1;
0179     }
0180
0181     /* Take away the IDSEL. */
0182     (void)ctx->board_pci_idsel(device, 0);
0183
0184     local_irq_restore(flags);
0185     return error;
0186 }
0187
0188 static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
0189                 int where,  u8 *val)
0190 {
0191     u32 data;
0192     int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
0193
0194     if (where & 1)
0195         data >>= 8;
0196     if (where & 2)
0197         data >>= 16;
0198     *val = data & 0xff;
0199     return ret;
0200 }
0201
0202 static int read_config_word(struct pci_bus *bus, unsigned int devfn,
0203                 int where, u16 *val)
0204 {
0205     u32 data;
0206     int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
0207
0208     if (where & 2)
0209         data >>= 16;
0210     *val = data & 0xffff;
0211     return ret;
0212 }
0213
0214 static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
0215                  int where, u32 *val)
0216 {
0217     return config_access(PCI_ACCESS_READ, bus, devfn, where, val);
0218 }
0219
0220 static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
0221                  int where, u8 val)
0222 {
0223     u32 data = 0;
0224
0225     if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
0226         return -1;
0227
0228     data = (data & ~(0xff << ((where & 3) << 3))) |
0229            (val << ((where & 3) << 3));
0230
0231     if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
0232         return -1;
0233
0234     return PCIBIOS_SUCCESSFUL;
0235 }
0236
0237 static int write_config_word(struct pci_bus *bus, unsigned int devfn,
0238                  int where, u16 val)
0239 {
0240     u32 data = 0;
0241
0242     if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
0243         return -1;
0244
0245     data = (data & ~(0xffff << ((where & 3) << 3))) |
0246            (val << ((where & 3) << 3));
0247
0248     if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
0249         return -1;
0250
0251     return PCIBIOS_SUCCESSFUL;
0252 }
0253
0254 static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
0255                   int where, u32 val)
0256 {
0257     return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val);
0258 }
0259
0260 static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn,
0261                int where, int size, u32 *val)
0262 {
0263     switch (size) {
0264     case 1: {
0265             u8 _val;
0266             int rc = read_config_byte(bus, devfn, where, &_val);
0267
0268             *val = _val;
0269             return rc;
0270         }
0271     case 2: {
0272             u16 _val;
0273             int rc = read_config_word(bus, devfn, where, &_val);
0274
0275             *val = _val;
0276             return rc;
0277         }
0278     default:
0279         return read_config_dword(bus, devfn, where, val);
0280     }
0281 }
0282
0283 static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn,
0284                  int where, int size, u32 val)
0285 {
0286     switch (size) {
0287     case 1:
0288         return write_config_byte(bus, devfn, where, (u8) val);
0289     case 2:
0290         return write_config_word(bus, devfn, where, (u16) val);
0291     default:
0292         return write_config_dword(bus, devfn, where, val);
0293     }
0294 }
0295
0296 static struct pci_ops alchemy_pci_ops = {
0297     .read   = alchemy_pci_read,
0298     .write  = alchemy_pci_write,
0299 };
0300
0301 static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
0302 {
0303     return 1;   /* success */
0304 }
0305
0306 /* save PCI controller register contents. */
0307 static int alchemy_pci_suspend(void)
0308 {
0309     struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
0310     if (!ctx)
0311         return 0;
0312
0313     ctx->pm[0]  = __raw_readl(ctx->regs + PCI_REG_CMEM);
0314     ctx->pm[1]  = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
0315     ctx->pm[2]  = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
0316     ctx->pm[3]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
0317     ctx->pm[4]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
0318     ctx->pm[5]  = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
0319     ctx->pm[6]  = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
0320     ctx->pm[7]  = __raw_readl(ctx->regs + PCI_REG_ID);
0321     ctx->pm[8]  = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
0322     ctx->pm[9]  = __raw_readl(ctx->regs + PCI_REG_PARAM);
0323     ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
0324     ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
0325
0326     return 0;
0327 }
0328
0329 static void alchemy_pci_resume(void)
0330 {
0331     struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
0332     if (!ctx)
0333         return;
0334
0335     __raw_writel(ctx->pm[0],  ctx->regs + PCI_REG_CMEM);
0336     __raw_writel(ctx->pm[2],  ctx->regs + PCI_REG_B2BMASK_CCH);
0337     __raw_writel(ctx->pm[3],  ctx->regs + PCI_REG_B2BBASE0_VID);
0338     __raw_writel(ctx->pm[4],  ctx->regs + PCI_REG_B2BBASE1_SID);
0339     __raw_writel(ctx->pm[5],  ctx->regs + PCI_REG_MWMASK_DEV);
0340     __raw_writel(ctx->pm[6],  ctx->regs + PCI_REG_MWBASE_REV_CCL);
0341     __raw_writel(ctx->pm[7],  ctx->regs + PCI_REG_ID);
0342     __raw_writel(ctx->pm[8],  ctx->regs + PCI_REG_CLASSREV);
0343     __raw_writel(ctx->pm[9],  ctx->regs + PCI_REG_PARAM);
0344     __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
0345     __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
0346     wmb();
0347     __raw_writel(ctx->pm[1],  ctx->regs + PCI_REG_CONFIG);
0348     wmb();
0349
0350     /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
0351      * on resume, making it necessary to recreate it as soon as possible.
0352      */
0353     ctx->wired_entry = 8191;    /* impossibly high value */
0354     alchemy_pci_wired_entry(ctx);   /* install it */
0355 }
0356
0357 static struct syscore_ops alchemy_pci_pmops = {
0358     .suspend    = alchemy_pci_suspend,
0359     .resume     = alchemy_pci_resume,
0360 };
0361
0362 static int alchemy_pci_probe(struct platform_device *pdev)
0363 {
0364     struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
0365     struct alchemy_pci_context *ctx;
0366     void __iomem *virt_io;
0367     unsigned long val;
0368     struct resource *r;
0369     struct clk *c;
0370     int ret;
0371
0372     /* need at least PCI IRQ mapping table */
0373     if (!pd) {
0374         dev_err(&pdev->dev, "need platform data for PCI setup\n");
0375         ret = -ENODEV;
0376         goto out;
0377     }
0378
0379     ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
0380     if (!ctx) {
0381         dev_err(&pdev->dev, "no memory for pcictl context\n");
0382         ret = -ENOMEM;
0383         goto out;
0384     }
0385
0386     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0387     if (!r) {
0388         dev_err(&pdev->dev, "no  pcictl ctrl regs resource\n");
0389         ret = -ENODEV;
0390         goto out1;
0391     }
0392
0393     if (!request_mem_region(r->start, resource_size(r), pdev->name)) {
0394         dev_err(&pdev->dev, "cannot claim pci regs\n");
0395         ret = -ENODEV;
0396         goto out1;
0397     }
0398
0399     c = clk_get(&pdev->dev, "pci_clko");
0400     if (IS_ERR(c)) {
0401         dev_err(&pdev->dev, "unable to find PCI clock\n");
0402         ret = PTR_ERR(c);
0403         goto out2;
0404     }
0405
0406     ret = clk_prepare_enable(c);
0407     if (ret) {
0408         dev_err(&pdev->dev, "cannot enable PCI clock\n");
0409         goto out6;
0410     }
0411
0412     ctx->regs = ioremap(r->start, resource_size(r));
0413     if (!ctx->regs) {
0414         dev_err(&pdev->dev, "cannot map pci regs\n");
0415         ret = -ENODEV;
0416         goto out5;
0417     }
0418
0419     /* map parts of the PCI IO area */
0420     /* REVISIT: if this changes with a newer variant (doubt it) make this
0421      * a platform resource.
0422      */
0423     virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000);
0424     if (!virt_io) {
0425         dev_err(&pdev->dev, "cannot remap pci io space\n");
0426         ret = -ENODEV;
0427         goto out3;
0428     }
0429     ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
0430
0431     /* Au1500 revisions older than AD have borked coherent PCI */
0432     if (alchemy_get_cputype() == ALCHEMY_CPU_AU1500 &&
0433         read_c0_prid() < 0x01030202 && !dma_default_coherent) {
0434         val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
0435         val |= PCI_CONFIG_NC;
0436         __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
0437         wmb();
0438         dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n");
0439     }
0440
0441     if (pd->board_map_irq)
0442         ctx->board_map_irq = pd->board_map_irq;
0443
0444     if (pd->board_pci_idsel)
0445         ctx->board_pci_idsel = pd->board_pci_idsel;
0446     else
0447         ctx->board_pci_idsel = alchemy_pci_def_idsel;
0448
0449     /* fill in relevant pci_controller members */
0450     ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops;
0451     ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres;
0452     ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores;
0453
0454     /* we can't ioremap the entire pci config space because it's too large,
0455      * nor can we dynamically ioremap it because some drivers use the
0456      * PCI config routines from within atomic contex and that becomes a
0457      * problem in get_vm_area().  Instead we use one wired TLB entry to
0458      * handle all config accesses for all busses.
0459      */
0460     ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
0461     if (!ctx->pci_cfg_vm) {
0462         dev_err(&pdev->dev, "unable to get vm area\n");
0463         ret = -ENOMEM;
0464         goto out4;
0465     }
0466     ctx->wired_entry = 8191;    /* impossibly high value */
0467     alchemy_pci_wired_entry(ctx);   /* install it */
0468
0469     set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
0470
0471     /* board may want to modify bits in the config register, do it now */
0472     val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
0473     val &= ~pd->pci_cfg_clr;
0474     val |= pd->pci_cfg_set;
0475     val &= ~PCI_CONFIG_PD;      /* clear disable bit */
0476     __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
0477     wmb();
0478
0479     __alchemy_pci_ctx = ctx;
0480     platform_set_drvdata(pdev, ctx);
0481     register_syscore_ops(&alchemy_pci_pmops);
0482     register_pci_controller(&ctx->alchemy_pci_ctrl);
0483
0484     dev_info(&pdev->dev, "PCI controller at %ld MHz\n",
0485          clk_get_rate(c) / 1000000);
0486
0487     return 0;
0488
0489 out4:
0490     iounmap(virt_io);
0491 out3:
0492     iounmap(ctx->regs);
0493 out5:
0494     clk_disable_unprepare(c);
0495 out6:
0496     clk_put(c);
0497 out2:
0498     release_mem_region(r->start, resource_size(r));
0499 out1:
0500     kfree(ctx);
0501 out:
0502     return ret;
0503 }
0504
0505 static struct platform_driver alchemy_pcictl_driver = {
0506     .probe      = alchemy_pci_probe,
0507     .driver = {
0508         .name   = "alchemy-pci",
0509     },
0510 };
0511
0512 static int __init alchemy_pci_init(void)
0513 {
0514     /* Au1500/Au1550 have PCI */
0515     switch (alchemy_get_cputype()) {
0516     case ALCHEMY_CPU_AU1500:
0517     case ALCHEMY_CPU_AU1550:
0518         return platform_driver_register(&alchemy_pcictl_driver);
0519     }
0520     return 0;
0521 }
0522 arch_initcall(alchemy_pci_init);
0523
0524
0525 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0526 {
0527     struct alchemy_pci_context *ctx = dev->sysdata;
0528     if (ctx && ctx->board_map_irq)
0529         return ctx->board_map_irq(dev, slot, pin);
0530     return -1;
0531 }
0532
0533 int pcibios_plat_dev_init(struct pci_dev *dev)
0534 {
0535     return 0;
0536 }