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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
0004  *
0005  * Based on linux/arch/mips/pci/ops-tx4938.c,
0006  *      linux/arch/mips/pci/fixup-rbtx4938.c,
0007  *      linux/arch/mips/txx9/rbtx4938/setup.c,
0008  *      and RBTX49xx patch from CELF patch archive.
0009  *
0010  * 2003-2005 (c) MontaVista Software, Inc.
0011  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
0012  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
0013  */
0014 #include <linux/kernel.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/irq.h>
0017 #include <asm/txx9/pci.h>
0018 #include <asm/txx9/tx4927pcic.h>
0019 
0020 static struct {
0021     struct pci_controller *channel;
0022     struct tx4927_pcic_reg __iomem *pcicptr;
0023 } pcicptrs[2];  /* TX4938 has 2 pcic */
0024 
0025 static void __init set_tx4927_pcicptr(struct pci_controller *channel,
0026                       struct tx4927_pcic_reg __iomem *pcicptr)
0027 {
0028     int i;
0029 
0030     for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
0031         if (pcicptrs[i].channel == channel) {
0032             pcicptrs[i].pcicptr = pcicptr;
0033             return;
0034         }
0035     }
0036     for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
0037         if (!pcicptrs[i].channel) {
0038             pcicptrs[i].channel = channel;
0039             pcicptrs[i].pcicptr = pcicptr;
0040             return;
0041         }
0042     }
0043     BUG();
0044 }
0045 
0046 struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
0047     struct pci_controller *channel)
0048 {
0049     int i;
0050 
0051     for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
0052         if (pcicptrs[i].channel == channel)
0053             return pcicptrs[i].pcicptr;
0054     }
0055     return NULL;
0056 }
0057 
0058 static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
0059           struct tx4927_pcic_reg __iomem *pcicptr)
0060 {
0061     if (bus->parent == NULL &&
0062         devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
0063         return -1;
0064     __raw_writel(((bus->number & 0xff) << 0x10)
0065              | ((devfn & 0xff) << 0x08) | (where & 0xfc)
0066              | (bus->parent ? 1 : 0),
0067              &pcicptr->g2pcfgadrs);
0068     /* clear M_ABORT and Disable M_ABORT Int. */
0069     __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
0070              | (PCI_STATUS_REC_MASTER_ABORT << 16),
0071              &pcicptr->pcistatus);
0072     return 0;
0073 }
0074 
0075 static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
0076 {
0077     int code = PCIBIOS_SUCCESSFUL;
0078 
0079     /* wait write cycle completion before checking error status */
0080     while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
0081         ;
0082     if (__raw_readl(&pcicptr->pcistatus)
0083         & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
0084         __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
0085                  | (PCI_STATUS_REC_MASTER_ABORT << 16),
0086                  &pcicptr->pcistatus);
0087         /* flush write buffer */
0088         iob();
0089         code = PCIBIOS_DEVICE_NOT_FOUND;
0090     }
0091     return code;
0092 }
0093 
0094 static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
0095 {
0096 #ifdef __BIG_ENDIAN
0097     offset ^= 3;
0098 #endif
0099     return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
0100 }
0101 static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
0102 {
0103 #ifdef __BIG_ENDIAN
0104     offset ^= 2;
0105 #endif
0106     return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
0107 }
0108 static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
0109 {
0110     return __raw_readl(&pcicptr->g2pcfgdata);
0111 }
0112 static void icd_writeb(u8 val, int offset,
0113                struct tx4927_pcic_reg __iomem *pcicptr)
0114 {
0115 #ifdef __BIG_ENDIAN
0116     offset ^= 3;
0117 #endif
0118     __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
0119 }
0120 static void icd_writew(u16 val, int offset,
0121                struct tx4927_pcic_reg __iomem *pcicptr)
0122 {
0123 #ifdef __BIG_ENDIAN
0124     offset ^= 2;
0125 #endif
0126     __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
0127 }
0128 static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
0129 {
0130     __raw_writel(val, &pcicptr->g2pcfgdata);
0131 }
0132 
0133 static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
0134 {
0135     struct pci_controller *channel = bus->sysdata;
0136     return get_tx4927_pcicptr(channel);
0137 }
0138 
0139 static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
0140                   int where, int size, u32 *val)
0141 {
0142     struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
0143 
0144     if (mkaddr(bus, devfn, where, pcicptr)) {
0145         *val = 0xffffffff;
0146         return -1;
0147     }
0148     switch (size) {
0149     case 1:
0150         *val = icd_readb(where & 3, pcicptr);
0151         break;
0152     case 2:
0153         *val = icd_readw(where & 3, pcicptr);
0154         break;
0155     default:
0156         *val = icd_readl(pcicptr);
0157     }
0158     return check_abort(pcicptr);
0159 }
0160 
0161 static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
0162                    int where, int size, u32 val)
0163 {
0164     struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
0165 
0166     if (mkaddr(bus, devfn, where, pcicptr))
0167         return -1;
0168     switch (size) {
0169     case 1:
0170         icd_writeb(val, where & 3, pcicptr);
0171         break;
0172     case 2:
0173         icd_writew(val, where & 3, pcicptr);
0174         break;
0175     default:
0176         icd_writel(val, pcicptr);
0177     }
0178     return check_abort(pcicptr);
0179 }
0180 
0181 static struct pci_ops tx4927_pci_ops = {
0182     .read = tx4927_pci_config_read,
0183     .write = tx4927_pci_config_write,
0184 };
0185 
0186 static struct {
0187     u8 trdyto;
0188     u8 retryto;
0189     u16 gbwc;
0190 } tx4927_pci_opts = {
0191     .trdyto = 0,
0192     .retryto = 0,
0193     .gbwc = 0xfe0,  /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
0194 };
0195 
0196 char *tx4927_pcibios_setup(char *str)
0197 {
0198     if (!strncmp(str, "trdyto=", 7)) {
0199         u8 val = 0;
0200         if (kstrtou8(str + 7, 0, &val) == 0)
0201             tx4927_pci_opts.trdyto = val;
0202         return NULL;
0203     }
0204     if (!strncmp(str, "retryto=", 8)) {
0205         u8 val = 0;
0206         if (kstrtou8(str + 8, 0, &val) == 0)
0207             tx4927_pci_opts.retryto = val;
0208         return NULL;
0209     }
0210     if (!strncmp(str, "gbwc=", 5)) {
0211         u16 val;
0212         if (kstrtou16(str + 5, 0, &val) == 0)
0213             tx4927_pci_opts.gbwc = val;
0214         return NULL;
0215     }
0216     return str;
0217 }
0218 
0219 void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
0220                   struct pci_controller *channel, int extarb)
0221 {
0222     int i;
0223     unsigned long flags;
0224 
0225     set_tx4927_pcicptr(channel, pcicptr);
0226 
0227     if (!channel->pci_ops)
0228         printk(KERN_INFO
0229                "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
0230                __raw_readl(&pcicptr->pciid) >> 16,
0231                __raw_readl(&pcicptr->pciid) & 0xffff,
0232                __raw_readl(&pcicptr->pciccrev) & 0xff,
0233             extarb ? "External" : "Internal");
0234     channel->pci_ops = &tx4927_pci_ops;
0235 
0236     local_irq_save(flags);
0237 
0238     /* Disable All Initiator Space */
0239     __raw_writel(__raw_readl(&pcicptr->pciccfg)
0240              & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
0241              | TX4927_PCIC_PCICCFG_G2PMEN(1)
0242              | TX4927_PCIC_PCICCFG_G2PMEN(2)
0243              | TX4927_PCIC_PCICCFG_G2PIOEN),
0244              &pcicptr->pciccfg);
0245 
0246     /* GB->PCI mappings */
0247     __raw_writel((channel->io_resource->end - channel->io_resource->start)
0248              >> 4,
0249              &pcicptr->g2piomask);
0250     ____raw_writeq((channel->io_resource->start +
0251             channel->io_map_base - IO_BASE) |
0252 #ifdef __BIG_ENDIAN
0253                TX4927_PCIC_G2PIOGBASE_ECHG
0254 #else
0255                TX4927_PCIC_G2PIOGBASE_BSDIS
0256 #endif
0257                , &pcicptr->g2piogbase);
0258     ____raw_writeq(channel->io_resource->start - channel->io_offset,
0259                &pcicptr->g2piopbase);
0260     for (i = 0; i < 3; i++) {
0261         __raw_writel(0, &pcicptr->g2pmmask[i]);
0262         ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
0263         ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
0264     }
0265     if (channel->mem_resource->end) {
0266         __raw_writel((channel->mem_resource->end
0267                   - channel->mem_resource->start) >> 4,
0268                  &pcicptr->g2pmmask[0]);
0269         ____raw_writeq(channel->mem_resource->start |
0270 #ifdef __BIG_ENDIAN
0271                    TX4927_PCIC_G2PMnGBASE_ECHG
0272 #else
0273                    TX4927_PCIC_G2PMnGBASE_BSDIS
0274 #endif
0275                    , &pcicptr->g2pmgbase[0]);
0276         ____raw_writeq(channel->mem_resource->start -
0277                    channel->mem_offset,
0278                    &pcicptr->g2pmpbase[0]);
0279     }
0280     /* PCI->GB mappings (I/O 256B) */
0281     __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
0282     ____raw_writeq(0, &pcicptr->p2giogbase);
0283     /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
0284     __raw_writel(0, &pcicptr->p2gm0plbase);
0285     __raw_writel(0, &pcicptr->p2gm0pubase);
0286     ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
0287 #ifdef __BIG_ENDIAN
0288                TX4927_PCIC_P2GMnGBASE_TECHG
0289 #else
0290                TX4927_PCIC_P2GMnGBASE_TBSDIS
0291 #endif
0292                , &pcicptr->p2gmgbase[0]);
0293     /* PCI->GB mappings (MEM 16MB) */
0294     __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
0295     __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
0296     ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
0297     /* PCI->GB mappings (MEM 1MB) */
0298     __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
0299     ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
0300 
0301     /* Clear all (including IRBER) except for GBWC */
0302     __raw_writel((tx4927_pci_opts.gbwc << 16)
0303              & TX4927_PCIC_PCICCFG_GBWC_MASK,
0304              &pcicptr->pciccfg);
0305     /* Enable Initiator Memory Space */
0306     if (channel->mem_resource->end)
0307         __raw_writel(__raw_readl(&pcicptr->pciccfg)
0308                  | TX4927_PCIC_PCICCFG_G2PMEN(0),
0309                  &pcicptr->pciccfg);
0310     /* Enable Initiator I/O Space */
0311     if (channel->io_resource->end)
0312         __raw_writel(__raw_readl(&pcicptr->pciccfg)
0313                  | TX4927_PCIC_PCICCFG_G2PIOEN,
0314                  &pcicptr->pciccfg);
0315     /* Enable Initiator Config */
0316     __raw_writel(__raw_readl(&pcicptr->pciccfg)
0317              | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
0318              &pcicptr->pciccfg);
0319 
0320     /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
0321     __raw_writel(0, &pcicptr->pcicfg1);
0322 
0323     __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
0324              | (tx4927_pci_opts.trdyto & 0xff)
0325              | ((tx4927_pci_opts.retryto & 0xff) << 8),
0326              &pcicptr->g2ptocnt);
0327 
0328     /* Clear All Local Bus Status */
0329     __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
0330     /* Enable All Local Bus Interrupts */
0331     __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
0332     /* Clear All Initiator Status */
0333     __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
0334     /* Enable All Initiator Interrupts */
0335     __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
0336     /* Clear All PCI Status Error */
0337     __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
0338              | (TX4927_PCIC_PCISTATUS_ALL << 16),
0339              &pcicptr->pcistatus);
0340     /* Enable All PCI Status Error Interrupts */
0341     __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
0342 
0343     if (!extarb) {
0344         /* Reset Bus Arbiter */
0345         __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
0346         __raw_writel(0, &pcicptr->pbabm);
0347         /* Enable Bus Arbiter */
0348         __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
0349     }
0350 
0351     __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
0352              | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
0353              &pcicptr->pcistatus);
0354     local_irq_restore(flags);
0355 
0356     printk(KERN_DEBUG
0357            "PCI: COMMAND=%04x,PCIMASK=%04x,"
0358            "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
0359            __raw_readl(&pcicptr->pcistatus) & 0xffff,
0360            __raw_readl(&pcicptr->pcimask) & 0xffff,
0361            __raw_readl(&pcicptr->g2ptocnt) & 0xff,
0362            (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
0363            (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
0364 }
0365 
0366 static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
0367 {
0368     __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
0369     __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
0370     __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
0371     static struct {
0372         __u32 flag;
0373         const char *str;
0374     } pcistat_tbl[] = {
0375         { PCI_STATUS_DETECTED_PARITY,   "DetectedParityError" },
0376         { PCI_STATUS_SIG_SYSTEM_ERROR,  "SignaledSystemError" },
0377         { PCI_STATUS_REC_MASTER_ABORT,  "ReceivedMasterAbort" },
0378         { PCI_STATUS_REC_TARGET_ABORT,  "ReceivedTargetAbort" },
0379         { PCI_STATUS_SIG_TARGET_ABORT,  "SignaledTargetAbort" },
0380         { PCI_STATUS_PARITY,    "MasterParityError" },
0381     }, g2pstat_tbl[] = {
0382         { TX4927_PCIC_G2PSTATUS_TTOE,   "TIOE" },
0383         { TX4927_PCIC_G2PSTATUS_RTOE,   "RTOE" },
0384     }, pcicstat_tbl[] = {
0385         { TX4927_PCIC_PCICSTATUS_PME,   "PME" },
0386         { TX4927_PCIC_PCICSTATUS_TLB,   "TLB" },
0387         { TX4927_PCIC_PCICSTATUS_NIB,   "NIB" },
0388         { TX4927_PCIC_PCICSTATUS_ZIB,   "ZIB" },
0389         { TX4927_PCIC_PCICSTATUS_PERR,  "PERR" },
0390         { TX4927_PCIC_PCICSTATUS_SERR,  "SERR" },
0391         { TX4927_PCIC_PCICSTATUS_GBE,   "GBE" },
0392         { TX4927_PCIC_PCICSTATUS_IWB,   "IWB" },
0393     };
0394     int i, cont;
0395 
0396     printk(KERN_ERR "");
0397     if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
0398         printk(KERN_CONT "pcistat:%04x(", pcistatus);
0399         for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
0400             if (pcistatus & pcistat_tbl[i].flag)
0401                 printk(KERN_CONT "%s%s",
0402                        cont++ ? " " : "", pcistat_tbl[i].str);
0403         printk(KERN_CONT ") ");
0404     }
0405     if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
0406         printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
0407         for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
0408             if (g2pstatus & g2pstat_tbl[i].flag)
0409                 printk(KERN_CONT "%s%s",
0410                        cont++ ? " " : "", g2pstat_tbl[i].str);
0411         printk(KERN_CONT ") ");
0412     }
0413     if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
0414         printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
0415         for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
0416             if (pcicstatus & pcicstat_tbl[i].flag)
0417                 printk(KERN_CONT "%s%s",
0418                        cont++ ? " " : "", pcicstat_tbl[i].str);
0419         printk(KERN_CONT ")");
0420     }
0421     printk(KERN_CONT "\n");
0422 }
0423 
0424 void tx4927_report_pcic_status(void)
0425 {
0426     int i;
0427 
0428     for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
0429         if (pcicptrs[i].pcicptr)
0430             tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
0431     }
0432 }
0433 
0434 static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr)
0435 {
0436     int i;
0437     __u32 __iomem *preg = (__u32 __iomem *)pcicptr;
0438 
0439     printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr);
0440     for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) {
0441         if (i % 32 == 0) {
0442             printk(KERN_CONT "\n");
0443             printk(KERN_INFO "%04x:", i);
0444         }
0445         /* skip registers with side-effects */
0446         if (i == offsetof(struct tx4927_pcic_reg, g2pintack)
0447             || i == offsetof(struct tx4927_pcic_reg, g2pspc)
0448             || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs)
0449             || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) {
0450             printk(KERN_CONT " XXXXXXXX");
0451             continue;
0452         }
0453         printk(KERN_CONT " %08x", __raw_readl(preg));
0454     }
0455     printk(KERN_CONT "\n");
0456 }
0457 
0458 void tx4927_dump_pcic_settings(void)
0459 {
0460     int i;
0461 
0462     for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
0463         if (pcicptrs[i].pcicptr)
0464             tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr);
0465     }
0466 }
0467 
0468 irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
0469 {
0470     struct pt_regs *regs = get_irq_regs();
0471     struct tx4927_pcic_reg __iomem *pcicptr =
0472         (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id;
0473 
0474     if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
0475         printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n",
0476                (int)(2 * sizeof(unsigned long)), regs->cp0_epc);
0477         tx4927_report_pcic_status1(pcicptr);
0478     }
0479     if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
0480         /* clear all pci errors */
0481         __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
0482                  | (TX4927_PCIC_PCISTATUS_ALL << 16),
0483                  &pcicptr->pcistatus);
0484         __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
0485         __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus);
0486         __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
0487         return IRQ_HANDLED;
0488     }
0489     console_verbose();
0490     tx4927_dump_pcic_settings1(pcicptr);
0491     panic("PCI error.");
0492 }
0493 
0494 #ifdef CONFIG_TOSHIBA_FPCIB0
0495 static void tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
0496 {
0497     struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
0498 
0499     if (!pcicptr)
0500         return;
0501     if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
0502         /* Reset Bus Arbiter */
0503         __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
0504         /*
0505          * swap reqBP and reqXP (raise priority of SLC90E66).
0506          * SLC90E66(PCI-ISA bridge) is connected to REQ2 on
0507          * PCI Backplane board.
0508          */
0509         __raw_writel(0x72543610, &pcicptr->pbareqport);
0510         __raw_writel(0, &pcicptr->pbabm);
0511         /* Use Fixed ParkMaster (required by SLC90E66) */
0512         __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
0513         /* Enable Bus Arbiter */
0514         __raw_writel(TX4927_PCIC_PBACFG_FIXPA |
0515                  TX4927_PCIC_PBACFG_PBAEN,
0516                  &pcicptr->pbacfg);
0517         printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n",
0518                __raw_readl(&pcicptr->pbareqport));
0519     }
0520 }
0521 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
0522 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
0523     tx4927_quirk_slc90e66_bridge);
0524 #endif
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