mips/pci/ops-bcm63xx.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
0007  */
0008
0009 #include <linux/types.h>
0010 #include <linux/pci.h>
0011 #include <linux/kernel.h>
0012 #include <linux/delay.h>
0013 #include <linux/io.h>
0014
0015 #include "pci-bcm63xx.h"
0016
0017 /*
0018  * swizzle 32bits data to return only the needed part
0019  */
0020 static int postprocess_read(u32 data, int where, unsigned int size)
0021 {
0022     u32 ret;
0023
0024     ret = 0;
0025     switch (size) {
0026     case 1:
0027         ret = (data >> ((where & 3) << 3)) & 0xff;
0028         break;
0029     case 2:
0030         ret = (data >> ((where & 3) << 3)) & 0xffff;
0031         break;
0032     case 4:
0033         ret = data;
0034         break;
0035     }
0036     return ret;
0037 }
0038
0039 static int preprocess_write(u32 orig_data, u32 val, int where,
0040                 unsigned int size)
0041 {
0042     u32 ret;
0043
0044     ret = 0;
0045     switch (size) {
0046     case 1:
0047         ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
0048             (val << ((where & 3) << 3));
0049         break;
0050     case 2:
0051         ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
0052             (val << ((where & 3) << 3));
0053         break;
0054     case 4:
0055         ret = val;
0056         break;
0057     }
0058     return ret;
0059 }
0060
0061 /*
0062  * setup hardware for a configuration cycle with given parameters
0063  */
0064 static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
0065                     unsigned int devfn, int where)
0066 {
0067     unsigned int slot, func, reg;
0068     u32 val;
0069
0070     slot = PCI_SLOT(devfn);
0071     func = PCI_FUNC(devfn);
0072     reg = where >> 2;
0073
0074     /* sanity check */
0075     if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
0076         return 1;
0077
0078     if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
0079         return 1;
0080
0081     if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
0082         return 1;
0083
0084     /* ok, setup config access */
0085     val = (reg << MPI_L2PCFG_REG_SHIFT);
0086     val |= (func << MPI_L2PCFG_FUNC_SHIFT);
0087     val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
0088     val |= MPI_L2PCFG_CFG_USEREG_MASK;
0089     val |= MPI_L2PCFG_CFG_SEL_MASK;
0090     /* type 0 cycle for local bus, type 1 cycle for anything else */
0091     if (type != 0) {
0092         /* FIXME: how to specify bus ??? */
0093         val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
0094     }
0095     bcm_mpi_writel(val, MPI_L2PCFG_REG);
0096
0097     return 0;
0098 }
0099
0100 static int bcm63xx_do_cfg_read(int type, unsigned int busn,
0101                 unsigned int devfn, int where, int size,
0102                 u32 *val)
0103 {
0104     u32 data;
0105
0106     /* two phase cycle, first we write address, then read data at
0107      * another location, caller already has a spinlock so no need
0108      * to add one here  */
0109     if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
0110         return PCIBIOS_DEVICE_NOT_FOUND;
0111     iob();
0112     data = le32_to_cpu(__raw_readl(pci_iospace_start));
0113     /* restore IO space normal behaviour */
0114     bcm_mpi_writel(0, MPI_L2PCFG_REG);
0115
0116     *val = postprocess_read(data, where, size);
0117
0118     return PCIBIOS_SUCCESSFUL;
0119 }
0120
0121 static int bcm63xx_do_cfg_write(int type, unsigned int busn,
0122                  unsigned int devfn, int where, int size,
0123                  u32 val)
0124 {
0125     u32 data;
0126
0127     /* two phase cycle, first we write address, then write data to
0128      * another location, caller already has a spinlock so no need
0129      * to add one here  */
0130     if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
0131         return PCIBIOS_DEVICE_NOT_FOUND;
0132     iob();
0133
0134     data = le32_to_cpu(__raw_readl(pci_iospace_start));
0135     data = preprocess_write(data, val, where, size);
0136
0137     __raw_writel(cpu_to_le32(data), pci_iospace_start);
0138     wmb();
0139     /* no way to know the access is done, we have to wait */
0140     udelay(500);
0141     /* restore IO space normal behaviour */
0142     bcm_mpi_writel(0, MPI_L2PCFG_REG);
0143
0144     return PCIBIOS_SUCCESSFUL;
0145 }
0146
0147 static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
0148                  int where, int size, u32 *val)
0149 {
0150     int type;
0151
0152     type = bus->parent ? 1 : 0;
0153
0154     if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
0155         return PCIBIOS_DEVICE_NOT_FOUND;
0156
0157     return bcm63xx_do_cfg_read(type, bus->number, devfn,
0158                     where, size, val);
0159 }
0160
0161 static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
0162                   int where, int size, u32 val)
0163 {
0164     int type;
0165
0166     type = bus->parent ? 1 : 0;
0167
0168     if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
0169         return PCIBIOS_DEVICE_NOT_FOUND;
0170
0171     return bcm63xx_do_cfg_write(type, bus->number, devfn,
0172                      where, size, val);
0173 }
0174
0175 struct pci_ops bcm63xx_pci_ops = {
0176     .read   = bcm63xx_pci_read,
0177     .write  = bcm63xx_pci_write
0178 };
0179
0180 #ifdef CONFIG_CARDBUS
0181 /*
0182  * emulate configuration read access on a cardbus bridge
0183  */
0184 #define FAKE_CB_BRIDGE_SLOT 0x1e
0185
0186 static int fake_cb_bridge_bus_number = -1;
0187
0188 static struct {
0189     u16 pci_command;
0190     u8 cb_latency;
0191     u8 subordinate_busn;
0192     u8 cardbus_busn;
0193     u8 pci_busn;
0194     int bus_assigned;
0195     u16 bridge_control;
0196
0197     u32 mem_base0;
0198     u32 mem_limit0;
0199     u32 mem_base1;
0200     u32 mem_limit1;
0201
0202     u32 io_base0;
0203     u32 io_limit0;
0204     u32 io_base1;
0205     u32 io_limit1;
0206 } fake_cb_bridge_regs;
0207
0208 static int fake_cb_bridge_read(int where, int size, u32 *val)
0209 {
0210     unsigned int reg;
0211     u32 data;
0212
0213     data = 0;
0214     reg = where >> 2;
0215     switch (reg) {
0216     case (PCI_VENDOR_ID >> 2):
0217     case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
0218         /* create dummy vendor/device id from our cpu id */
0219         data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM;
0220         break;
0221
0222     case (PCI_COMMAND >> 2):
0223         data = (PCI_STATUS_DEVSEL_SLOW << 16);
0224         data |= fake_cb_bridge_regs.pci_command;
0225         break;
0226
0227     case (PCI_CLASS_REVISION >> 2):
0228         data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
0229         break;
0230
0231     case (PCI_CACHE_LINE_SIZE >> 2):
0232         data = (PCI_HEADER_TYPE_CARDBUS << 16);
0233         break;
0234
0235     case (PCI_INTERRUPT_LINE >> 2):
0236         /* bridge control */
0237         data = (fake_cb_bridge_regs.bridge_control << 16);
0238         /* pin:intA line:0xff */
0239         data |= (0x1 << 8) | 0xff;
0240         break;
0241
0242     case (PCI_CB_PRIMARY_BUS >> 2):
0243         data = (fake_cb_bridge_regs.cb_latency << 24);
0244         data |= (fake_cb_bridge_regs.subordinate_busn << 16);
0245         data |= (fake_cb_bridge_regs.cardbus_busn << 8);
0246         data |= fake_cb_bridge_regs.pci_busn;
0247         break;
0248
0249     case (PCI_CB_MEMORY_BASE_0 >> 2):
0250         data = fake_cb_bridge_regs.mem_base0;
0251         break;
0252
0253     case (PCI_CB_MEMORY_LIMIT_0 >> 2):
0254         data = fake_cb_bridge_regs.mem_limit0;
0255         break;
0256
0257     case (PCI_CB_MEMORY_BASE_1 >> 2):
0258         data = fake_cb_bridge_regs.mem_base1;
0259         break;
0260
0261     case (PCI_CB_MEMORY_LIMIT_1 >> 2):
0262         data = fake_cb_bridge_regs.mem_limit1;
0263         break;
0264
0265     case (PCI_CB_IO_BASE_0 >> 2):
0266         /* | 1 for 32bits io support */
0267         data = fake_cb_bridge_regs.io_base0 | 0x1;
0268         break;
0269
0270     case (PCI_CB_IO_LIMIT_0 >> 2):
0271         data = fake_cb_bridge_regs.io_limit0;
0272         break;
0273
0274     case (PCI_CB_IO_BASE_1 >> 2):
0275         /* | 1 for 32bits io support */
0276         data = fake_cb_bridge_regs.io_base1 | 0x1;
0277         break;
0278
0279     case (PCI_CB_IO_LIMIT_1 >> 2):
0280         data = fake_cb_bridge_regs.io_limit1;
0281         break;
0282     }
0283
0284     *val = postprocess_read(data, where, size);
0285     return PCIBIOS_SUCCESSFUL;
0286 }
0287
0288 /*
0289  * emulate configuration write access on a cardbus bridge
0290  */
0291 static int fake_cb_bridge_write(int where, int size, u32 val)
0292 {
0293     unsigned int reg;
0294     u32 data, tmp;
0295     int ret;
0296
0297     ret = fake_cb_bridge_read((where & ~0x3), 4, &data);
0298     if (ret != PCIBIOS_SUCCESSFUL)
0299         return ret;
0300
0301     data = preprocess_write(data, val, where, size);
0302
0303     reg = where >> 2;
0304     switch (reg) {
0305     case (PCI_COMMAND >> 2):
0306         fake_cb_bridge_regs.pci_command = (data & 0xffff);
0307         break;
0308
0309     case (PCI_CB_PRIMARY_BUS >> 2):
0310         fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
0311         fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
0312         fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
0313         fake_cb_bridge_regs.pci_busn = data & 0xff;
0314         if (fake_cb_bridge_regs.cardbus_busn)
0315             fake_cb_bridge_regs.bus_assigned = 1;
0316         break;
0317
0318     case (PCI_INTERRUPT_LINE >> 2):
0319         tmp = (data >> 16) & 0xffff;
0320         /* disable memory prefetch support */
0321         tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
0322         tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
0323         fake_cb_bridge_regs.bridge_control = tmp;
0324         break;
0325
0326     case (PCI_CB_MEMORY_BASE_0 >> 2):
0327         fake_cb_bridge_regs.mem_base0 = data;
0328         break;
0329
0330     case (PCI_CB_MEMORY_LIMIT_0 >> 2):
0331         fake_cb_bridge_regs.mem_limit0 = data;
0332         break;
0333
0334     case (PCI_CB_MEMORY_BASE_1 >> 2):
0335         fake_cb_bridge_regs.mem_base1 = data;
0336         break;
0337
0338     case (PCI_CB_MEMORY_LIMIT_1 >> 2):
0339         fake_cb_bridge_regs.mem_limit1 = data;
0340         break;
0341
0342     case (PCI_CB_IO_BASE_0 >> 2):
0343         fake_cb_bridge_regs.io_base0 = data;
0344         break;
0345
0346     case (PCI_CB_IO_LIMIT_0 >> 2):
0347         fake_cb_bridge_regs.io_limit0 = data;
0348         break;
0349
0350     case (PCI_CB_IO_BASE_1 >> 2):
0351         fake_cb_bridge_regs.io_base1 = data;
0352         break;
0353
0354     case (PCI_CB_IO_LIMIT_1 >> 2):
0355         fake_cb_bridge_regs.io_limit1 = data;
0356         break;
0357     }
0358
0359     return PCIBIOS_SUCCESSFUL;
0360 }
0361
0362 static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
0363                int where, int size, u32 *val)
0364 {
0365     /* snoop access to slot 0x1e on root bus, we fake a cardbus
0366      * bridge at this location */
0367     if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
0368         fake_cb_bridge_bus_number = bus->number;
0369         return fake_cb_bridge_read(where, size, val);
0370     }
0371
0372     /* a  configuration  cycle for  the  device  behind the  cardbus
0373      * bridge is  actually done as a  type 0 cycle  on the primary
0374      * bus. This means that only  one device can be on the cardbus
0375      * bus */
0376     if (fake_cb_bridge_regs.bus_assigned &&
0377         bus->number == fake_cb_bridge_regs.cardbus_busn &&
0378         PCI_SLOT(devfn) == 0)
0379         return bcm63xx_do_cfg_read(0, 0,
0380                        PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
0381                        where, size, val);
0382
0383     return PCIBIOS_DEVICE_NOT_FOUND;
0384 }
0385
0386 static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
0387                 int where, int size, u32 val)
0388 {
0389     if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
0390         fake_cb_bridge_bus_number = bus->number;
0391         return fake_cb_bridge_write(where, size, val);
0392     }
0393
0394     if (fake_cb_bridge_regs.bus_assigned &&
0395         bus->number == fake_cb_bridge_regs.cardbus_busn &&
0396         PCI_SLOT(devfn) == 0)
0397         return bcm63xx_do_cfg_write(0, 0,
0398                         PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
0399                         where, size, val);
0400
0401     return PCIBIOS_DEVICE_NOT_FOUND;
0402 }
0403
0404 struct pci_ops bcm63xx_cb_ops = {
0405     .read   = bcm63xx_cb_read,
0406     .write   = bcm63xx_cb_write,
0407 };
0408
0409 /*
0410  * only one IO window, so it  cannot be shared by PCI and cardbus, use
0411  * fixup to choose and detect unhandled configuration
0412  */
0413 static void bcm63xx_fixup(struct pci_dev *dev)
0414 {
0415     static int io_window = -1;
0416     int i, found, new_io_window;
0417     u32 val;
0418
0419     /* look for any io resource */
0420     found = 0;
0421     for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
0422         if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
0423             found = 1;
0424             break;
0425         }
0426     }
0427
0428     if (!found)
0429         return;
0430
0431     /* skip our fake bus with only cardbus bridge on it */
0432     if (dev->bus->number == fake_cb_bridge_bus_number)
0433         return;
0434
0435     /* find on which bus the device is */
0436     if (fake_cb_bridge_regs.bus_assigned &&
0437         dev->bus->number == fake_cb_bridge_regs.cardbus_busn &&
0438         PCI_SLOT(dev->devfn) == 0)
0439         new_io_window = 1;
0440     else
0441         new_io_window = 0;
0442
0443     if (new_io_window == io_window)
0444         return;
0445
0446     if (io_window != -1) {
0447         printk(KERN_ERR "bcm63xx: both PCI and cardbus devices "
0448                "need IO, which hardware cannot do\n");
0449         return;
0450     }
0451
0452     printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n",
0453            (new_io_window == 0) ? "PCI" : "cardbus");
0454
0455     val = bcm_mpi_readl(MPI_L2PIOREMAP_REG);
0456     if (io_window)
0457         val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
0458     else
0459         val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
0460     bcm_mpi_writel(val, MPI_L2PIOREMAP_REG);
0461
0462     io_window = new_io_window;
0463 }
0464
0465 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
0466 #endif
0467
0468 static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
0469 {
0470     switch (bus->number) {
0471     case PCIE_BUS_BRIDGE:
0472         return PCI_SLOT(devfn) == 0;
0473     case PCIE_BUS_DEVICE:
0474         if (PCI_SLOT(devfn) == 0)
0475             return bcm_pcie_readl(PCIE_DLSTATUS_REG)
0476                     & DLSTATUS_PHYLINKUP;
0477         fallthrough;
0478     default:
0479         return false;
0480     }
0481 }
0482
0483 static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
0484                  int where, int size, u32 *val)
0485 {
0486     u32 data;
0487     u32 reg = where & ~3;
0488
0489     if (!bcm63xx_pcie_can_access(bus, devfn))
0490         return PCIBIOS_DEVICE_NOT_FOUND;
0491
0492     if (bus->number == PCIE_BUS_DEVICE)
0493         reg += PCIE_DEVICE_OFFSET;
0494
0495     data = bcm_pcie_readl(reg);
0496
0497     *val = postprocess_read(data, where, size);
0498
0499     return PCIBIOS_SUCCESSFUL;
0500
0501 }
0502
0503 static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
0504                   int where, int size, u32 val)
0505 {
0506     u32 data;
0507     u32 reg = where & ~3;
0508
0509     if (!bcm63xx_pcie_can_access(bus, devfn))
0510         return PCIBIOS_DEVICE_NOT_FOUND;
0511
0512     if (bus->number == PCIE_BUS_DEVICE)
0513         reg += PCIE_DEVICE_OFFSET;
0514
0515
0516     data = bcm_pcie_readl(reg);
0517
0518     data = preprocess_write(data, val, where, size);
0519     bcm_pcie_writel(data, reg);
0520
0521     return PCIBIOS_SUCCESSFUL;
0522 }
0523
0524
0525 struct pci_ops bcm63xx_pcie_ops = {
0526     .read   = bcm63xx_pcie_read,
0527     .write  = bcm63xx_pcie_write
0528 };