mips/pci/msi-octeon.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2005-2009, 2010 Cavium Networks
0007  */
0008 #include <linux/kernel.h>
0009 #include <linux/init.h>
0010 #include <linux/msi.h>
0011 #include <linux/spinlock.h>
0012 #include <linux/interrupt.h>
0013
0014 #include <asm/octeon/octeon.h>
0015 #include <asm/octeon/cvmx-npi-defs.h>
0016 #include <asm/octeon/cvmx-pci-defs.h>
0017 #include <asm/octeon/cvmx-npei-defs.h>
0018 #include <asm/octeon/cvmx-sli-defs.h>
0019 #include <asm/octeon/cvmx-pexp-defs.h>
0020 #include <asm/octeon/pci-octeon.h>
0021
0022 /*
0023  * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
0024  * in use.
0025  */
0026 static u64 msi_free_irq_bitmask[4];
0027
0028 /*
0029  * Each bit in msi_multiple_irq_bitmask tells that the device using
0030  * this bit in msi_free_irq_bitmask is also using the next bit. This
0031  * is used so we can disable all of the MSI interrupts when a device
0032  * uses multiple.
0033  */
0034 static u64 msi_multiple_irq_bitmask[4];
0035
0036 /*
0037  * This lock controls updates to msi_free_irq_bitmask and
0038  * msi_multiple_irq_bitmask.
0039  */
0040 static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
0041
0042 /*
0043  * Number of MSI IRQs used. This variable is set up in
0044  * the module init time.
0045  */
0046 static int msi_irq_size;
0047
0048 /**
0049  * arch_setup_msi_irq() - setup MSI IRQs for a device
0050  * @dev:    Device requesting MSI interrupts
0051  * @desc:   MSI descriptor
0052  *
0053  * Called when a driver requests MSI interrupts instead of the
0054  * legacy INT A-D. This routine will allocate multiple interrupts
0055  * for MSI devices that support them. A device can override this by
0056  * programming the MSI control bits [6:4] before calling
0057  * pci_enable_msi().
0058  *
0059  * Return: %0 on success, non-%0 on error.
0060  */
0061 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
0062 {
0063     struct msi_msg msg;
0064     u16 control;
0065     int configured_private_bits;
0066     int request_private_bits;
0067     int irq = 0;
0068     int irq_step;
0069     u64 search_mask;
0070     int index;
0071
0072     if (desc->pci.msi_attrib.is_msix)
0073         return -EINVAL;
0074
0075     /*
0076      * Read the MSI config to figure out how many IRQs this device
0077      * wants.  Most devices only want 1, which will give
0078      * configured_private_bits and request_private_bits equal 0.
0079      */
0080     pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
0081
0082     /*
0083      * If the number of private bits has been configured then use
0084      * that value instead of the requested number. This gives the
0085      * driver the chance to override the number of interrupts
0086      * before calling pci_enable_msi().
0087      */
0088     configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
0089     if (configured_private_bits == 0) {
0090         /* Nothing is configured, so use the hardware requested size */
0091         request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
0092     } else {
0093         /*
0094          * Use the number of configured bits, assuming the
0095          * driver wanted to override the hardware request
0096          * value.
0097          */
0098         request_private_bits = configured_private_bits;
0099     }
0100
0101     /*
0102      * The PCI 2.3 spec mandates that there are at most 32
0103      * interrupts. If this device asks for more, only give it one.
0104      */
0105     if (request_private_bits > 5)
0106         request_private_bits = 0;
0107
0108 try_only_one:
0109     /*
0110      * The IRQs have to be aligned on a power of two based on the
0111      * number being requested.
0112      */
0113     irq_step = 1 << request_private_bits;
0114
0115     /* Mask with one bit for each IRQ */
0116     search_mask = (1 << irq_step) - 1;
0117
0118     /*
0119      * We're going to search msi_free_irq_bitmask_lock for zero
0120      * bits. This represents an MSI interrupt number that isn't in
0121      * use.
0122      */
0123     spin_lock(&msi_free_irq_bitmask_lock);
0124     for (index = 0; index < msi_irq_size/64; index++) {
0125         for (irq = 0; irq < 64; irq += irq_step) {
0126             if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) {
0127                 msi_free_irq_bitmask[index] |= search_mask << irq;
0128                 msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq;
0129                 goto msi_irq_allocated;
0130             }
0131         }
0132     }
0133 msi_irq_allocated:
0134     spin_unlock(&msi_free_irq_bitmask_lock);
0135
0136     /* Make sure the search for available interrupts didn't fail */
0137     if (irq >= 64) {
0138         if (request_private_bits) {
0139             pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one",
0140                    1 << request_private_bits);
0141             request_private_bits = 0;
0142             goto try_only_one;
0143         } else
0144             panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");
0145     }
0146
0147     /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
0148     irq += index*64;
0149     irq += OCTEON_IRQ_MSI_BIT0;
0150
0151     switch (octeon_dma_bar_type) {
0152     case OCTEON_DMA_BAR_TYPE_SMALL:
0153         /* When not using big bar, Bar 0 is based at 128MB */
0154         msg.address_lo =
0155             ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
0156         msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
0157         break;
0158     case OCTEON_DMA_BAR_TYPE_BIG:
0159         /* When using big bar, Bar 0 is based at 0 */
0160         msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
0161         msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
0162         break;
0163     case OCTEON_DMA_BAR_TYPE_PCIE:
0164         /* When using PCIe, Bar 0 is based at 0 */
0165         /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
0166         msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
0167         msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
0168         break;
0169     case OCTEON_DMA_BAR_TYPE_PCIE2:
0170         /* When using PCIe2, Bar 0 is based at 0 */
0171         msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;
0172         msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;
0173         break;
0174     default:
0175         panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
0176     }
0177     msg.data = irq - OCTEON_IRQ_MSI_BIT0;
0178
0179     /* Update the number of IRQs the device has available to it */
0180     control &= ~PCI_MSI_FLAGS_QSIZE;
0181     control |= request_private_bits << 4;
0182     pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
0183
0184     irq_set_msi_desc(irq, desc);
0185     pci_write_msi_msg(irq, &msg);
0186     return 0;
0187 }
0188
0189 /**
0190  * arch_teardown_msi_irq() - release MSI IRQs for a device
0191  * @irq:    The devices first irq number. There may be multiple in sequence.
0192  *
0193  * Called when a device no longer needs its MSI interrupts. All
0194  * MSI interrupts for the device are freed.
0195  */
0196 void arch_teardown_msi_irq(unsigned int irq)
0197 {
0198     int number_irqs;
0199     u64 bitmask;
0200     int index = 0;
0201     int irq0;
0202
0203     if ((irq < OCTEON_IRQ_MSI_BIT0)
0204         || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0))
0205         panic("arch_teardown_msi_irq: Attempted to teardown illegal "
0206               "MSI interrupt (%d)", irq);
0207
0208     irq -= OCTEON_IRQ_MSI_BIT0;
0209     index = irq / 64;
0210     irq0 = irq % 64;
0211
0212     /*
0213      * Count the number of IRQs we need to free by looking at the
0214      * msi_multiple_irq_bitmask. Each bit set means that the next
0215      * IRQ is also owned by this device.
0216      */
0217     number_irqs = 0;
0218     while ((irq0 + number_irqs < 64) &&
0219            (msi_multiple_irq_bitmask[index]
0220         & (1ull << (irq0 + number_irqs))))
0221         number_irqs++;
0222     number_irqs++;
0223     /* Mask with one bit for each IRQ */
0224     bitmask = (1 << number_irqs) - 1;
0225     /* Shift the mask to the correct bit location */
0226     bitmask <<= irq0;
0227     if ((msi_free_irq_bitmask[index] & bitmask) != bitmask)
0228         panic("arch_teardown_msi_irq: Attempted to teardown MSI "
0229               "interrupt (%d) not in use", irq);
0230
0231     /* Checks are done, update the in use bitmask */
0232     spin_lock(&msi_free_irq_bitmask_lock);
0233     msi_free_irq_bitmask[index] &= ~bitmask;
0234     msi_multiple_irq_bitmask[index] &= ~bitmask;
0235     spin_unlock(&msi_free_irq_bitmask_lock);
0236 }
0237
0238 static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
0239
0240 static u64 msi_rcv_reg[4];
0241 static u64 mis_ena_reg[4];
0242
0243 static void octeon_irq_msi_enable_pcie(struct irq_data *data)
0244 {
0245     u64 en;
0246     unsigned long flags;
0247     int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
0248     int irq_index = msi_number >> 6;
0249     int irq_bit = msi_number & 0x3f;
0250
0251     raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
0252     en = cvmx_read_csr(mis_ena_reg[irq_index]);
0253     en |= 1ull << irq_bit;
0254     cvmx_write_csr(mis_ena_reg[irq_index], en);
0255     cvmx_read_csr(mis_ena_reg[irq_index]);
0256     raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
0257 }
0258
0259 static void octeon_irq_msi_disable_pcie(struct irq_data *data)
0260 {
0261     u64 en;
0262     unsigned long flags;
0263     int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
0264     int irq_index = msi_number >> 6;
0265     int irq_bit = msi_number & 0x3f;
0266
0267     raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
0268     en = cvmx_read_csr(mis_ena_reg[irq_index]);
0269     en &= ~(1ull << irq_bit);
0270     cvmx_write_csr(mis_ena_reg[irq_index], en);
0271     cvmx_read_csr(mis_ena_reg[irq_index]);
0272     raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
0273 }
0274
0275 static struct irq_chip octeon_irq_chip_msi_pcie = {
0276     .name = "MSI",
0277     .irq_enable = octeon_irq_msi_enable_pcie,
0278     .irq_disable = octeon_irq_msi_disable_pcie,
0279 };
0280
0281 static void octeon_irq_msi_enable_pci(struct irq_data *data)
0282 {
0283     /*
0284      * Octeon PCI doesn't have the ability to mask/unmask MSI
0285      * interrupts individually. Instead of masking/unmasking them
0286      * in groups of 16, we simple assume MSI devices are well
0287      * behaved. MSI interrupts are always enable and the ACK is
0288      * assumed to be enough
0289      */
0290 }
0291
0292 static void octeon_irq_msi_disable_pci(struct irq_data *data)
0293 {
0294     /* See comment in enable */
0295 }
0296
0297 static struct irq_chip octeon_irq_chip_msi_pci = {
0298     .name = "MSI",
0299     .irq_enable = octeon_irq_msi_enable_pci,
0300     .irq_disable = octeon_irq_msi_disable_pci,
0301 };
0302
0303 /*
0304  * Called by the interrupt handling code when an MSI interrupt
0305  * occurs.
0306  */
0307 static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits)
0308 {
0309     int irq;
0310     int bit;
0311
0312     bit = fls64(msi_bits);
0313     if (bit) {
0314         bit--;
0315         /* Acknowledge it first. */
0316         cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);
0317
0318         irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index;
0319         do_IRQ(irq);
0320         return IRQ_HANDLED;
0321     }
0322     return IRQ_NONE;
0323 }
0324
0325 #define OCTEON_MSI_INT_HANDLER_X(x)                 \
0326 static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id)   \
0327 {                                   \
0328     u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]);         \
0329     return __octeon_msi_do_interrupt((x), msi_bits);        \
0330 }
0331
0332 /*
0333  * Create octeon_msi_interrupt{0-3} function body
0334  */
0335 OCTEON_MSI_INT_HANDLER_X(0);
0336 OCTEON_MSI_INT_HANDLER_X(1);
0337 OCTEON_MSI_INT_HANDLER_X(2);
0338 OCTEON_MSI_INT_HANDLER_X(3);
0339
0340 /*
0341  * Initializes the MSI interrupt handling code
0342  */
0343 int __init octeon_msi_initialize(void)
0344 {
0345     int irq;
0346     struct irq_chip *msi;
0347
0348     if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_INVALID) {
0349         return 0;
0350     } else if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
0351         msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
0352         msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
0353         msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
0354         msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3;
0355         mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0;
0356         mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1;
0357         mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2;
0358         mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3;
0359         msi = &octeon_irq_chip_msi_pcie;
0360     } else {
0361         msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV;
0362 #define INVALID_GENERATE_ADE 0x8700000000000000ULL;
0363         msi_rcv_reg[1] = INVALID_GENERATE_ADE;
0364         msi_rcv_reg[2] = INVALID_GENERATE_ADE;
0365         msi_rcv_reg[3] = INVALID_GENERATE_ADE;
0366         mis_ena_reg[0] = INVALID_GENERATE_ADE;
0367         mis_ena_reg[1] = INVALID_GENERATE_ADE;
0368         mis_ena_reg[2] = INVALID_GENERATE_ADE;
0369         mis_ena_reg[3] = INVALID_GENERATE_ADE;
0370         msi = &octeon_irq_chip_msi_pci;
0371     }
0372
0373     for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
0374         irq_set_chip_and_handler(irq, msi, handle_simple_irq);
0375
0376     if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
0377         if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
0378                 0, "MSI[0:63]", octeon_msi_interrupt0))
0379             panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
0380
0381         if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1,
0382                 0, "MSI[64:127]", octeon_msi_interrupt1))
0383             panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
0384
0385         if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2,
0386                 0, "MSI[127:191]", octeon_msi_interrupt2))
0387             panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
0388
0389         if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3,
0390                 0, "MSI[192:255]", octeon_msi_interrupt3))
0391             panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
0392
0393         msi_irq_size = 256;
0394     } else if (octeon_is_pci_host()) {
0395         if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
0396                 0, "MSI[0:15]", octeon_msi_interrupt0))
0397             panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
0398
0399         if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0,
0400                 0, "MSI[16:31]", octeon_msi_interrupt0))
0401             panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
0402
0403         if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0,
0404                 0, "MSI[32:47]", octeon_msi_interrupt0))
0405             panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
0406
0407         if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0,
0408                 0, "MSI[48:63]", octeon_msi_interrupt0))
0409             panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
0410         msi_irq_size = 64;
0411     }
0412     return 0;
0413 }
0414 subsys_initcall(octeon_msi_initialize);