mips/pci/fixup-malta.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/init.h>
0003 #include <linux/pci.h>
0004 #include <asm/mips-boards/piix4.h>
0005
0006 /* PCI interrupt pins */
0007 #define PCIA        1
0008 #define PCIB        2
0009 #define PCIC        3
0010 #define PCID        4
0011
0012 /* This table is filled in by interrogating the PIIX4 chip */
0013 static char pci_irq[5] = {
0014 };
0015
0016 static char irq_tab[][5] = {
0017     /*  INTA    INTB    INTC    INTD */
0018     {0, 0,  0,  0,  0 },    /*  0: GT64120 PCI bridge */
0019     {0, 0,  0,  0,  0 },    /*  1: Unused */
0020     {0, 0,  0,  0,  0 },    /*  2: Unused */
0021     {0, 0,  0,  0,  0 },    /*  3: Unused */
0022     {0, 0,  0,  0,  0 },    /*  4: Unused */
0023     {0, 0,  0,  0,  0 },    /*  5: Unused */
0024     {0, 0,  0,  0,  0 },    /*  6: Unused */
0025     {0, 0,  0,  0,  0 },    /*  7: Unused */
0026     {0, 0,  0,  0,  0 },    /*  8: Unused */
0027     {0, 0,  0,  0,  0 },    /*  9: Unused */
0028     {0, 0,  0,  0,  PCID }, /* 10: PIIX4 USB */
0029     {0, PCIB,   0,  0,  0 },    /* 11: AMD 79C973 Ethernet */
0030     {0, PCIC,   0,  0,  0 },    /* 12: Crystal 4281 Sound */
0031     {0, 0,  0,  0,  0 },    /* 13: Unused */
0032     {0, 0,  0,  0,  0 },    /* 14: Unused */
0033     {0, 0,  0,  0,  0 },    /* 15: Unused */
0034     {0, 0,  0,  0,  0 },    /* 16: Unused */
0035     {0, 0,  0,  0,  0 },    /* 17: Bonito/SOC-it PCI Bridge*/
0036     {0, PCIA,   PCIB,   PCIC,   PCID }, /* 18: PCI Slot 1 */
0037     {0, PCIB,   PCIC,   PCID,   PCIA }, /* 19: PCI Slot 2 */
0038     {0, PCIC,   PCID,   PCIA,   PCIB }, /* 20: PCI Slot 3 */
0039     {0, PCID,   PCIA,   PCIB,   PCIC }  /* 21: PCI Slot 4 */
0040 };
0041
0042 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0043 {
0044     int virq;
0045     virq = irq_tab[slot][pin];
0046     return pci_irq[virq];
0047 }
0048
0049 /* Do platform specific device initialization at pci_enable_device() time */
0050 int pcibios_plat_dev_init(struct pci_dev *dev)
0051 {
0052     return 0;
0053 }
0054
0055 static void malta_piix_func3_base_fixup(struct pci_dev *dev)
0056 {
0057     /* Set a sane PM I/O base address */
0058     pci_write_config_word(dev, PIIX4_FUNC3_PMBA, 0x1000);
0059
0060     /* Enable access to the PM I/O region */
0061     pci_write_config_byte(dev, PIIX4_FUNC3_PMREGMISC,
0062                   PIIX4_FUNC3_PMREGMISC_EN);
0063 }
0064
0065 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
0066             malta_piix_func3_base_fixup);
0067
0068 static void malta_piix_func0_fixup(struct pci_dev *pdev)
0069 {
0070     unsigned char reg_val;
0071     u32 reg_val32;
0072     u16 reg_val16;
0073     /* PIIX PIRQC[A:D] irq mappings */
0074     static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
0075         0,  0,  0,  3,
0076         4,  5,  6,  7,
0077         0,  9, 10, 11,
0078         12, 0, 14, 15
0079     };
0080     int i;
0081
0082     /* Interrogate PIIX4 to get PCI IRQ mapping */
0083     for (i = 0; i <= 3; i++) {
0084         pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val);
0085         if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE)
0086             pci_irq[PCIA+i] = 0;    /* Disabled */
0087         else
0088             pci_irq[PCIA+i] = piixirqmap[reg_val &
0089                 PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK];
0090     }
0091
0092     /* Done by YAMON 2.00 onwards */
0093     if (PCI_SLOT(pdev->devfn) == 10) {
0094         /*
0095          * Set top of main memory accessible by ISA or DMA
0096          * devices to 16 Mb.
0097          */
0098         pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val);
0099         pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
0100                 PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
0101     }
0102
0103     /* Mux SERIRQ to its pin */
0104     pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, &reg_val32);
0105     pci_write_config_dword(pdev, PIIX4_FUNC0_GENCFG,
0106                    reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ);
0107
0108     /* Enable SERIRQ */
0109     pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
0110     reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
0111     pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
0112
0113     /* Enable response to special cycles */
0114     pci_read_config_word(pdev, PCI_COMMAND, &reg_val16);
0115     pci_write_config_word(pdev, PCI_COMMAND,
0116                   reg_val16 | PCI_COMMAND_SPECIAL);
0117 }
0118
0119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
0120      malta_piix_func0_fixup);
0121
0122 static void malta_piix_func1_fixup(struct pci_dev *pdev)
0123 {
0124     unsigned char reg_val;
0125
0126     /* Done by YAMON 2.02 onwards */
0127     if (PCI_SLOT(pdev->devfn) == 10) {
0128         /*
0129          * IDE Decode enable.
0130          */
0131         pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
0132             &reg_val);
0133         pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
0134             reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN);
0135         pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
0136             &reg_val);
0137         pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
0138             reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN);
0139     }
0140 }
0141
0142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
0143      malta_piix_func1_fixup);
0144
0145 /* Enable PCI 2.1 compatibility in PIIX4 */
0146 static void quirk_dlcsetup(struct pci_dev *dev)
0147 {
0148     u8 odlc, ndlc;
0149
0150     (void) pci_read_config_byte(dev, PIIX4_FUNC0_DLC, &odlc);
0151     /* Enable passive releases and delayed transaction */
0152     ndlc = odlc | PIIX4_FUNC0_DLC_USBPR_EN |
0153               PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN |
0154               PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN;
0155     (void) pci_write_config_byte(dev, PIIX4_FUNC0_DLC, ndlc);
0156 }
0157
0158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
0159     quirk_dlcsetup);